The Fast Factorized Back Pro jection (FFBP) algorithm is a computationally efficient

algorithm for image formation in a Very High Frequency Synthetic Aperture Radar (VHF

SAR) system. In this report an investigation of the feasibility of using an FPGA with a

hard CPU core to calculate the FFBP in real-time has been done. Two System on a Chip

designs for this task have been proposed for calculating the FFBP. A simplified version of

the FFBP has also been implemented in Matlab and used during this pro ject. The result

is that the computationally intensive parts, such as index generating and interpolation

calculations, should be implemented in the logic part of the FPGA and the CPU should

handle scheduling. This kind of modular system is easy to maintain and upgrade.