Elementary functions are challenging to implement with correct ac-curacy. The inverse square root is one of the hardest elementary func-tions to implement with an accuracy that meets the requirements ofa faithful rounded operation. Multiplicative methods tend to haverounding problems when implementing an elementary function, whilstiterative methods are better off when rounding. The problem withmultiplicative methods lies in the accumulation of rounding errorsduring multiplication steps, which can lead to a loss of precision andinaccurate results. Iterative methods, on the other hand, can be morerobust against rounding errors because they primarily involve addi-tion and subtraction operations, which are less susceptible to preci-sion issues.In this thesis, we propose a novel method based on HarmonizedParabolic Synthesis, which combines parabolic synthesis and second-degree interpolation for implementing an inverse square root unitthat meets the single-precision format requirement of 1 ULP.The experimental results show that the proposed implementationdemonstrates improved resource usage and latency results when com-pared to other works (including Intel IP). Most of the implemen-tations that are compared have a similar throughput, whilst somehave a higher throughput than ours. In order to make HarmonizedParabolic Synthesis compatible with the IEEE-754 format for single-precision numbers, the number of intervals has to be increased. Wecan achieve the requirement of a faithful rounded operation with 256intervals. No optimization of the coefficients was required to achieveit.The throughput is measured in FLOP(Floating Point Operation)and in this thesis we achieve 1 FLOP per cycle. In this thesis we donot achieve good error properties due that the error distribution isnot around zero.The proposed implementation shows a 69.72% reduction in resourceus- age and a 69.52% decrease in latency compared to Intel’s IP. Dueto the small size, low latency and high throughput, the presentedfloating-point inverse square root unit is suitable for high-performanceembedded systems. It can be integrated into a processor’s floatingpoint unit or be used as a stand-alone accelerator.