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  • 51.
    Nilsson, Björn
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Free2Move, Halmstad, Sweden.
    Bengtsson, Lars
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Chalmers university of technology, Gothenburg, Sweden.
    Wiberg, Per-Arne
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Free2Move, Halmstad, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    The Effect of Introducing Carrier Sense in an Active RFID Protocol2007Report (Other academic)
    Abstract [en]

    Active Radio Frequency Identification (A-RFID) extends the functionality from the predecessor passive RFID trough adding a power source to the transponder device (device used on a product to identify it). This power source enables more advanced functions in the radio interface such as listening (doing a carrier sense) to the radio channel (carrier of data information) finding out if it is unengaged, and free to use. In this paper we study the carrier sense functionality and its effects in lowering the tag energy consumption. Simulation results show that the life time of a tag, in an A-RFID system, using carrier sense is more than doubled compared to one not using carrier sense. The increased lifetime of the tag is due to the lowered energy consumption caused by the improved throughput and the decreased payload delay, which in turn is thanks to using carrier sense and naturally then give a better utilization of the radio channel.

  • 52.
    Nilsson, Emil
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Nilsson, Björn
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Bengtsson, Lars
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Wiberg, Per-Arne
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Bilstrup, Urban
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A low power-long range active RFID-system consisting of active RFID backscatter transponders2010In: 2010 IEEE International Conference on RFID-Technology and Applications (RFID-TA), Piscataway, N.J.: IEEE Press, 2010, p. 26-30Conference paper (Refereed)
    Abstract [en]

    In this paper we present a novel active radio frequency identification system consisting of transponders with low complexity, low power consumption, and long system reading range. The transponder’s low complexity and small circuit integration area indicate that the production cost is comparable to the one of a passive tag. The hardware keystone is the transponder’s radio wake-up transceiver, which is a single oscillator with very low power consumption. The communication protocol, based on frequency signalling binary tree, contributes to the low complexity of the tag architecture. More than 1500 tags can be read per second. The average transponder ID read-out delay is 319 ms when there are 1000 transponders within reach of the interrogator. The calculated expected life time for a transponder is estimated to be almost three years.

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    FULLTEXT01
  • 53.
    Nilsson, Kenneth
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Department of Computer Engineering, Chalmers University of Technology, Göteborg, Sweden.
    Wiberg, Per-Arne
    Department of Computer Engineering, Chalmers University of Technology, Göteborg, Sweden.
    A modular, massively parallel computer architecture for trainable real-time control systems1993In: Control Engineering Practice, ISSN 0967-0661, E-ISSN 1873-6939, Vol. 1, no 4, p. 655-661Article in journal (Refereed)
    Abstract [en]

    A new system-architectural concept for trainable real-time control systems is based on resource adequacy both in processing and communication. Cyclically executing programs in distributed nodes communicate via a shared high-speed medium. Static scheduling of programs and communication implies that the maximum possible work-load can always be handled in a time-deterministic manner. The use of Artificial Neural Networks (ANN) algorithms and trainability implies a new system development strategy based on a Continuous Development paradigm. An implementation of the Architectural concept is presented. The communication speed is measured in Gbps and the access method is TDMA. An implementation of the system-development strategy is also presented. © 1993.

  • 54.
    Nilsson, Kenneth
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Wiberg, Per-Arne
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    A modular, massively-parallel computer architecture for trainable real-time control-systems1992In: ALGORITHMS AND ARCHITECTURES FOR REAL-TIME CONTROL (KOREA, 1992) / [ed] Fleming, P.J. and Kwon, W.H., Oxford: Pergamon Press, 1992, p. 43-48Conference paper (Other academic)
  • 55.
    Nordström, Tomas
    et al.
    Division of Computer Science and Engineering, Department of Systems Engineering, Luleå University of Technology, Luleå, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Using and designing massively parallel computers for artificial neural networks1992In: Journal of Parallel and Distributed Computing, ISSN 0743-7315, E-ISSN 1096-0848, Vol. 14, no 3, p. 260-285Article, review/survey (Refereed)
  • 56.
    Parsapoor, Mahboobeh
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). School of Computer Science, Faculty of Engineering & Physical Science, The University of Manchester, Manchester, United Kingdom.
    Bilstrup, Urban
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Brain Emotional Learning-based Prediction Model for the Prediction of Geomagnetic Storms2014In: Proceedings of the 2014 Federated Conference on Computer Science and Information Systems, Los Alamitos, CA: IEEE Press, 2014, p. 35-42Conference paper (Refereed)
    Abstract [en]

    This paper introduces a new type of brain emotional learning inspired models (BELIMs). The suggested model is  utilized as a suitable model for predicting geomagnetic storms. The model is known as BELPM which is an acronym for Brain Emotional Learning-based Prediction Model. The structure of the suggested model consists of four main parts and mimics the corresponding regions of the neural structure underlying fear conditioning. The functions of these parts are implemented by assigning adaptive networks to the different parts. The learning algorithm of BELPM is based on the steepest descent (SD) and the least square estimator (LSE). In this paper, BELPM is employed to predict geomagnetic storms using the Disturbance Storm Time (Dst) index. To evaluate the performance of BELPM, the obtained results have been compared with the results of the adaptive neuro-fuzzy inference system (ANFIS). © 2014 Polish Information Processing Society.

  • 57.
    Parsapoor, Mahboobeh
    et al.
    McGill University, Montreal, QC H3A 2T6, Canada.
    Bilstrup, Urban
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Forecasting Solar Activity with Computational Intelligence Models2018In: IEEE Access, E-ISSN 2169-3536, Vol. 6, p. 70902-70909Article in journal (Refereed)
    Abstract [en]

    It is vital to accurately predict solar activity, in order to decrease the plausible damage of electronic equipment in the event of a large high-intensity solar eruption. Recently, we have proposed brain emotional learning-based fuzzy inference system (BELFIS) as a tool for the forecasting of chaotic systems. The structure of BELFIS is designed based on the neural structure of fear conditioning. The function of BELFIS is implemented by assigning adaptive networks to the components of the BELFIS structure. This paper especially focuses on the performance evaluation of BELFIS as a predictor by forecasting solar cycles 16-24. The performance of BELFIS is compared with other computational models used for this purpose, in particular with the adaptive neuro-fuzzy inference system. © 2018 IEEE.

  • 58.
    Parsapoor, Mahboobeh
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). School of Computer Science, Faculty of Engineering & Physical Science, The University of Manchester, Manchester, United Kingdom.
    Bilstrup, Urban
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Neuro-fuzzy Models for Geomagnetic Storms Prediction: Using the Auroral Electrojet Index2014In: 2014 10th International Conference on Natural Computation (ICNC), Piscataway, NJ: IEEE Press, 2014, p. 12-17, article id 6975802Conference paper (Refereed)
    Abstract [en]

    This study presents comparative results obtained from employing four different neuro-fuzzy models to predict geomagnetic storms. Two of these neuro-fuzzy models can be classified as Brain Emotional Learning Inspired Models (BELIMs). These two models are BELFIS (Brain Emotional Learning Based Fuzzy Inference System) and BELRFS (Brain Emotional Learning Recurrent Fuzzy System). The two other models are Adaptive Neuro-Fuzzy Inference System (ANFIS) and Locally Linear Model Tree (LoLiMoT) learning algorithm, two powerful neuro-fuzzy models to accurately predict a nonlinear system. These models are compared for their ability to predict geomagnetic storms using the AE index.

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  • 59.
    Parsapoor, Mahboobeh
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). School of Computer Science, Faculty of Engineering & Physic al Science, The University of Manchester, Manchester, United Kingdom.
    Bilstrup, Urban
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Prediction of Solar Cycle 24: Using a Connectionist Model of the Emotional System2015In: 2015 International Joint Conference on Neural Networks (IJCNN), Piscataway, NJ: IEEE Press, 2015, article id 7280839Conference paper (Other (popular science, discussion, etc.))
    Abstract [en]

    Accurate prediction of solar activity as one aspect of space weather phenomena is essential to decrease the damage from these activities on the ground based communication, power grids, etc. Recently, the connectionist models of the brain such as neural networks and neuro-fuzzy methods have been proposed to forecast space weather phenomena; however, they have not been able to predict solar activity accurately. That has been a motivation for the development of the connectionist model of the brain; this paper aims to apply a connectionist model of the brain to accurately forecasting solar activity, in particular, solar cycle 24. The neuro-fuzzy method has been referred to as the brain emotional learning-based recurrent fuzzy system (BELRFS). BELRFS is tested for prediction of solar cycle 24, and the obtained results are compared with well-known neuro-fuzzy methods and neural networks as well as with physical-based methods. @2015 IEEE

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    fulltext
  • 60.
    Parsapoor, Mahboobeh
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Brooke, John Martin
    School of Computer Science, Faculty of Engineering and Physical Science, University of Manchester, Manchester, United Kingdom.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A new computational intelligence model for long-term prediction of solar and geomagnetic activity2015In: Proceedings of the Twenty-Ninth AAAI Conference on Artificial Intelligence, 2015, Vol. 6, p. 4192-4193Conference paper (Refereed)
    Abstract [en]

    This paper briefly describes how the neural structure of fear conditioning has inspired to develop a computational intelligence model that is referred to as the brain emotional learning-inspired model (BELIM). The model is applied to predict long step ahead of solar activity and geomagnetic storms. © Copyright 2015, Association for the Advancement of Artificial Intelligence (www.aaai.org). All rights reserved.

  • 61.
    Rögnvaldsson, Thorsteinn
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Brink, Joachim
    Halmstad University.
    Florén, Henrik
    Halmstad University, School of Business, Innovation and Sustainability, Centre for Innovation, Entrepreneurship and Learning Research (CIEL).
    Gaspes, Veronica
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Holmgren, Noél
    University of Skövde, Skövde, Sweden.
    Lutz, Mareike
    Halmstad University.
    Nilsson, Pernilla
    Halmstad University, School of Education, Humanities and Social Science, Research on Education and Learning within the Department of Teacher Education (FULL).
    Olsfelt, Jonas
    Halmstad University.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Ericsson, Claes
    Halmstad University, School of Education, Humanities and Social Science, Research on Education and Learning within the Department of Teacher Education (FULL).
    Gustafsson, Linnea
    Halmstad University, School of Education, Humanities and Social Science, Contexts and Cultural Boundaries (KK).
    Hoveskog, Maya
    Halmstad University, School of Business, Innovation and Sustainability, Centre for Innovation, Entrepreneurship and Learning Research (CIEL).
    Hylander, Jonny
    Halmstad University, School of Business, Engineering and Science, Biological and Environmental Systems (BLESS).
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Nygren, Jens
    Halmstad University, School of Health and Welfare, Centre of Research on Welfare, Health and Sport (CVHI).
    Rosén, Bengt-Göran
    Halmstad University, School of Business, Engineering and Science, Mechanical Engineering and Industrial Design (MTEK).
    Sandberg, Mikael
    Halmstad University, School of Education, Humanities and Social Science, Center for Social Analysis (CESAM).
    Benner, Mats
    Lund University, Lund, Sweden.
    Berg, Martin
    Halmstad University, School of Education, Humanities and Social Science, Center for Social Analysis (CESAM).
    Bergvall, Patrik
    Halmstad University.
    Carlborg, Anna
    Halmstad University.
    Fleischer, Siegfried
    Halmstad University, School of Business, Engineering and Science, Biological and Environmental Systems (BLESS).
    Hållander, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Mattsson, Marie
    Halmstad University, School of Business, Engineering and Science, Biological and Environmental Systems (BLESS).
    Olsson, Charlotte
    Halmstad University, School of Business, Engineering and Science, Biological and Environmental Systems (BLESS).
    Pettersson, Håkan
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Rundquist, Jonas
    Halmstad University, School of Business, Innovation and Sustainability, Centre for Innovation, Entrepreneurship and Learning Research (CIEL).
    Sahlén, Göran
    Halmstad University, School of Business, Engineering and Science, Biological and Environmental Systems (BLESS).
    Waara, Sylvia
    Halmstad University, School of Business, Engineering and Science, Biological and Environmental Systems (BLESS).
    Weisner, Stefan
    Halmstad University, School of Business, Engineering and Science, Biological and Environmental Systems (BLESS).
    Werner, Sven
    Halmstad University, School of Business, Engineering and Science, Biological and Environmental Systems (BLESS).
    ARC13 – Assessment of Research and Coproduction: Reports from the assessment of all research at Halmstad University 20132014Report (Other (popular science, discussion, etc.))
    Abstract [en]

    During 2013, an evaluation of all the research conducted at Halmstad University was carried out. The purpose was to assess the quality of the research, coproduction, and collaboration in research, as well as the impact of the research. The evaluation was dubbed the Assessment of Research and Coproduction 2013, or ARC13. (Extract from Executive Summary)

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    ARC13
  • 62.
    Svensson, Bertil
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Ul-Abdin, Zain
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Using a CSP based programming model for reconfigurable processor arrays2008In: International Conference on Reconfigurable Computing and FPGAs, 2008. ReConFig '08, Los Alamitos, California: IEEE Computer Society, 2008, p. 343-348Conference paper (Refereed)
    Abstract [en]

    The growing trend towards adoption of flexible and heterogeneous, parallel computing architectures has increased the challenges faced by the programming community. We propose a method to program an emerging class of reconfigurable processor arrays by using the CSP based programming model of occam-pi. The paper describes the extension of an existing compiler platform to target such architectures. To evaluate the performance of the generated code, we present three implementations of the DCT algorithm. It is concluded that CSP appears to be a suitable computation model for programming a wide variety of reconfigurable architectures.

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    FULLTEXT01
  • 63.
    Svensson, Bertil
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ericsson, Per M.
    Saab AB (EDS), Gothenburg, Sweden.
    Åhlander, Anders
    Saab AB (EDS), Gothenburg, Sweden.
    Hoang Bengtsson, Hoai
    Viktoria Swedish ICT, Gothenburg, Sweden.
    Bengtsson, Jerker
    Saab AB (EDS), Gothenburg, Sweden.
    Gaspes, Veronica
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nordström, Tomas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Running Leap for Embedded Signal Processing to Future Parallel Platforms2014In: WISE'14: Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering, New York, NY: Association for Computing Machinery (ACM), 2014, p. 35-42Conference paper (Refereed)
    Abstract [en]

    This paper highlights the collaboration between industry and academia in research. It describes more than two decades of intensive development and research of new hardware and software platforms to support innovative, high-performance sensor systems with extremely high demands on embedded signal processing capability. The joint research can be seen as the run before a necessary jump to a new kind of computational platform based on parallelism. The collaboration has had several phases, starting with a focus on hardware, then on efficiency, later on software development, and finally on taking the jump and understanding the expected future. In the first part of the paper, these phases and their respective challenges and results are described. Then, in the second part, we reflect upon the motivation for collaboration between company and university, the roles of the partners, the experiences gained and the long-term effects on both sides. Copyright © 2014 ACM.

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  • 64.
    Taveniku, Mikael
    et al.
    Department of Computer Engineering, Chalmers University of Technology, Göteborg, Sweden & Ericsson Microwave Systems AB, Mölndal, Sweden.
    Åhlander, Anders
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Jonsson, Magnus
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    A multiple SIMD mesh architecture for multi-channel radar processing1996In: Proceedings of: ICSPAT'96, international conference on signal processing applications & technology, Boston MA, USA, October 7-10: Research report CCA (9602), Miller Freeman , 1996, p. 1421-1427Conference paper (Refereed)
    Abstract [en]

    In modern and future radar applications there are high demands on the signal processing chain in terms of computational power and generality. At the same time, there are hard size and power consumption constraints. This paper reports on a project whose aim is to find a good scalable computer architecture that is flexible, programmable and as general-purpose as possible without too much performance loss.

    The proposed architecture consists of multiple SIMD computing modules, each based on a number of small mesh arrays. The modules are fully programmable and work globally as a MIMD machine and locally as SIMD machines. The data network is modular and provides both high bandwidth capacity and fast response. It has a fiber-optic stars topology, and employs time and wavelength division multiplexing, together with a medium access method specially developed for real-time systems.

    In this paper, we use a radar system with 64 processing channels to illustrate the algorithms and the usage of the processor modules. We show that it is possible to use a machine, consisting of small mesh processor arrays forming larger modules, with good efficiency. The building blocks show good balance between computational power and I/O bandwidth, and the SIMD approach seems good from algorithm-mapping point of view.

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  • 65.
    Taveniku, Mikael
    et al.
    Department of Computer Engineering, Chalmers University of Technology S-412 96 Goteborg, Sweden - Ericsson Microwave Systems AB, S-431 84 Molndal, Sweden .
    Åhlander, Anders
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Jonsson, Magnus
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    The VEGA moderately parallel MIMD, moderately parallel SIMD, architecture for high performance array signal processing1998In: Proceedings of the first merged International Parallel Processing Symposium & Symposium on Parallel and Distributed Processing: March 30 - April 3, 1998 Orlando, Florida, Los Alamitos, Calif.: IEEE Computer Press , 1998, p. 226-232Conference paper (Refereed)
    Abstract [en]

    In array radar signal processing applications, the processing demands range from tens of GFLOPS to several TFLOPS. To address this, as well as the, size and power dissipation issues, a special purpose “array signal processing” architecture is proposed. We argue that a combined MIMD-SIMD system can give flexibility, scalability, and programmability as well as high computing density. The MIMD system level, where SIMD modules are interconnected by a fiber-optic real-time network, provides the high level flexibility while the SIMD module level provides the compute density. In this paper we evaluate different design alternatives and show how the VEGA architecture was derived. By examining the applications and the algorithms used, the SIMD mesh processor is found be sufficient. However, the smaller the meshes are the better is the flexibility and efficiency. Then, based on prototype VLSI implementations and on instruction statistics, we find that a relatively large pipelined processing element maximises the performance per area. It is thereby concluded that the small SIMD mesh processor array with powerful processing elements is the best choice. These observations are further exploited in the design of the single-chip SIMD processor array to be included in the MIMD-style overall system. The system scales from 6.4 GFLOPS to several TFLOPS peak performance.

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    FULLTEXT01
  • 66.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Gebrewahid, Essayas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Managing Dynamic Reconfiguration for Fault-tolerance on a Manycore Architecture2012In: Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012, New York, USA: IEEE Computer Society, 2012, p. 312-319, article id 6270657Conference paper (Refereed)
    Abstract [en]

    With the advent of manycore architectures comprising hundreds of processing elements, fault management has become a major challenge. We present an approach that uses the occam-pi language to manage the fault recovery mechanism on a new manycore architecture, the Platform 2012 (P2012). The approach is made possible by extending our previously developed compiler framework to compile occam-pi implementations to the P2012 architecture. We describe the techniques used to translate the salient features of the occam-pi language to the native programming model of the P2012 architecture. We demonstrate the applicability of the approach by an experimental case study, in which the DCT algorithm is implemented on a set of four processing elements. During run-time, some of the tasks are then relocated from assumed faulty processing elements to the faultless ones by means of dynamic reconfiguration of the hardware. The working of the demonstrator and the simulation results illustrate not only the feasibility of the approach but also how the use of higher-level abstractions simplifies the fault handling. © 2012 IEEE.

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  • 67.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing2016In: ACM Transactions on Reconfigurable Technology and Systems, ISSN 1936-7406, E-ISSN 1936-7414, Vol. 9, no 4, article id 24Article in journal (Refereed)
    Abstract [en]

    The future trend in microprocessors for the more advanced embedded systems is focusing on massively parallel reconfigurable architectures, consisting of heterogeneous ensembles of hundreds of processing elements communicating over a reconfigurable interconnection network. However, the mastering of low-level micro-architectural details involved in programming of such massively parallel platforms becomes too cumbersome, which limits their adoption in many applications. Thus there is a dire need of an approach to produce high-performance scalable implementations that harness the computational resources of the emerging reconfigurable platforms.This paper addresses the grand challenge of accessibility of these diverse reconfigurable platforms by suggesting the use of a high-level language, occam-pi, and developing a complete design flow for building, compiling, and generating machine code for heterogeneous coarse-grained hardware. We have evaluated the approach by implementing complex industrial case studies and three common signal processing algorithms. The results of the implemented case-studies suggest that the occam-pi language based approach, because of its well-defined semantics for expressing concurrency and reconfigurability, simplifies the development of applications employing run-time reconfigurable devices. The associated compiler framework ensures portability as well as the performance benefits across heterogeneous platforms.

  • 68.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Study of Design Efficiency with a High-Level Language for FPGAs2007In: Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Abstracts and CD-ROM, Piscataway, N.J.: IEEE Press, 2007, p. 1-7Conference paper (Refereed)
    Abstract [en]

    Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used for mapping computations to such architectures still require the knowledge about architectural details of the target device to extract efficiency. A study of the Mobius language and tools is presented in this paper, with a focus on generated hardware performance. A number of streaming and memory-intensive applications have been developed and the results have been compared with the corresponding implementations in VHDL and a behavioral hardware description language. Based upon experimental evidences, it is concluded that Mobius, a minimal parallel processing language targeted for reconfigurable architectures, enhances productivity in terms of design time and code maintainability without considerably compromising performance and resources.

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  • 69.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    An Evaluation of High-Performance Embedded Processing on MPPAs2013In: Proceedings: 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2013, Los Alamitos, California: IEEE Computer Society, 2013, p. 235-235, article id 6546032Conference paper (Refereed)
    Abstract [en]

    Embedded signal processing is facing the challenges of increased performance as well as to achieve energy efficiency. Massively parallel processor arrays (MPPAs) consisting of tens or hundreds of processing cores offer the possibility of meeting the growing performance demand in an energy efficient way by exploiting parallelism instead of scaling the clock frequency of a single powerful processor.

    In this paper, we evaluate two variants of MPPAs by implementing a significantly large case study, namely an autofocus criterion calculation, which is a key component in modern synthetic aperture radar systems. The implementation results from the two target architectures are compared on the basis of utilized resources, performance, and energy efficiency. The Ambric implementations demonstrate the usefulness of occam-pi based high-level language approach in utilizing hundreds of processors, whereas the Epiphany implementation reveals that energy-efficiency can be improved even further by a factors of 2-3 with respect to the Ambric implementations and can be achieved at high clock speeds. © 2013 IEEE.

  • 70.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing2009In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 33, no 3, p. 161-178Article in journal (Refereed)
    Abstract [en]

    In order to meet the increased computational demands of, e.g., multimedia applications, such as video processing in HDTV, and communication applications, such as baseband processing in telecommunication systems, the architectures of reconfigurable devices have evolved to coarse-grained compositions of functional units or program controlled processors, which are operated in a coordinated manner to improve performance and energy efficiency. In this survey we explore the field of coarse-grained reconfigurable computing on the basis of the hardware aspects of granularity, reconfigurability, and interconnection networks, and discuss the effects of these on energy related properties and scalability. We also consider the computation models that are being adopted for programming of such machines, models that expose the parallelism inherent in the application in order to achieve better performance. We classify the coarse-grained reconfigurable architectures into four categories and present some of the existing examples of these categories. Finally, we identify the emerging trends of introduction of asynchronous techniques at the architectural level and the use of nano-electronics from technological perspective in the reconfigurable computing discipline.

  • 71.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Occam-pi as a High-level Language for Coarse-Grained Reconfigurable Architectures2011In: IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, Washington, USA: IEEE Computer Society, 2011, p. 236-243Conference paper (Refereed)
    Abstract [en]

    Recently we proposed occam-pi as a high-levellanguage for programming coarse grained reconfigurable architectures. The constructs of occam-pi combine ideas from CSPand pi-calculus to facilitate expressing parallelism, communication, and reconfigurability. The feasability of this approachwas illustrated by developing a compiler framework to compile occam-pi implementations to the Ambric architecture. In this paper, we demonstrate the applicability of occam-pif or programing an array of functional units, eXtreme ProcessingPlatform (XPP). This is made possible by extending the compilerframework to target the XPP architecture, including automatic floating to fixed-point conversion. Different implementations of a FIR filter and a DCT algorithm were developed and evaluated on the basis of performance and resource consumption. The reported results reveal that the approach of using occam-pito program the category of coarse grained reconfigurable architectures appears to be promising. The resulting implementations are generally much superior to those programmed in C and comparable to those hand-coded in the low-level native language NML.

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  • 72.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Occam-pi for Programming of Massively Parallel Reconfigurable Architectures2012In: International Journal of Reconfigurable Computing, ISSN 1687-7195, E-ISSN 1687-7209, Vol. 2012, article id 504815Article in journal (Refereed)
    Abstract [en]

    Massively parallel reconfigurable architectures, which offer massive parallelism coupled with the capability of undergoing run-time reconfiguration, are gaining attention in order to meet the increased computational demands of high-performance embedded systems. We propose that the occam-pi language is used for programming of the category of massively parallel reconfigurable architectures. The salient properties of the occam-pi language are explicit concurrency with built-in mechanisms for interprocessor communication, provision for expressing dynamic parallelism, support for the expression of dynamic reconfigurations, and placement attributes. To evaluate the programming approach, a compiler framework was extended to support the language extensions in the occam-pi language and a backend was developed to target the Ambric array of processors. We present two case-studies; DCT implementation exploiting the reconfigurability feature of occam-pi and a significantly large autofocus criterion calculation based on the dynamic parallelism capability of the occam-pi language. The results of the implemented case studies suggest that the occam-pi -language-based approach simplifies the development of applications employing run-time reconfigurable devices without compromising the performance benefits. Copyright © 2012 Zain-ul-Abdin and Bertil Svensson.

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  • 73.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Synthetic-Aperture Radar Processing on a Manycore Architecture2012Conference paper (Refereed)
    Abstract [en]

    Synthetic-Aperture Radar (SAR) systems that are used to create high-resolution radar images from low-resolution aperture data require high computational performance. Manycore architectures are emerging to overcome the computational requirements of the complex radar signal processing.

    In this paper, we evaluate a manycore architecture namely Epiphany by implementing two significantly large case studies of fast factorized back-projection and autofocus criterion calculation, which are key components in modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of utilized resources and performance. The Epiphany implementations demonstrate the usefulness of the architecture for the streaming algorithm (autofocus criterion calculation) by achieving speedup of 8.9x with respect to the sequential implementation on Intel Core i7 processor while operating at a lower clock speed. On the other hand, for the memory-intensive algorithm (fast factorized back-projection), the Epiphany architecture shows moderate speedup in the order of 4.25x. The Epiphany implementations of the two algorithms are, respectively, 38x and 78x more energy-efficient.

  • 74.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Towards Teaching Embedded Parallel Computing: An Analytical Approach2015In: Workshop on Computer Architecture Education, WCAE 2015, 2015Conference paper (Refereed)
    Abstract [en]

    Embedded electronic systems are finding increased applications in our daily life. In order to meet the application demands in embedded systems, parallel computing is used. This paper emphasizes teaching of the specific issues of parallel computing that are critical to embedded systems. We propose an analytical approach to deliver declarative and functioning knowledge for learning in the field of computer science and engineering with a special focus on Embedded Parallel Computing (EPC). We describe the teaching of a course with a focus on how parallel computing can be used to enhance performance and improve energy efficiency of embedded systems. The teaching methods include interactive lectures with web-based course literature, seminars, and lab exercises and home-assigned practical tasks. Further, the course is intended to give a general insight into current research and development in regard to parallel architectures and computation models. Since the course is an advanced level course, the students are expected to have a basic knowledge about the fundamentals of computer architecture and their common programming methodologies. The course puts emphasis on hands-on experience with embedded parallel computing. Therefore it includes an extensive laboratory and project part, in which a state of the art manycore embedded computing system is used. We believe that undertaking these methods in succession will prepare the students for both research as well as professional career. © 2015 ACM.

  • 75.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Åhlander, Anders
    Saab AB, Gothenburg, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Energy-Efficient Synthetic-Aperture Radar Processing on a Manycore Architecture2013In: Proceedings: International Conference on Parallel Processing : The 42nd Annual Conference : ICPP 2013 : 1-4 October 2013 : Lyon, France / [ed] Randall Bilof, Piscataway, NJ: IEEE conference proceedings, 2013, p. 330-338, article id 6687366Conference paper (Refereed)
    Abstract [en]

    The next generation radar systems have high performance demands on the signal processing chain. Examples include the advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in realtime. Manycore architectures are gaining attention as a means to overcome the computational requirements of the complex radar signal processing by exploiting massive parallelism inherent in the algorithms in an energy efficient manner.

    In this paper, we evaluate a manycore architecture, namely a 16-core Epiphany processor, by implementing two significantly large case studies, viz. an autofocus criterion calculation and the fast factorized back-projection algorithm, both key componentsin modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance and programmability. One of the Epiphany implementations demonstrates the usefulness of the architecture for the streaming based algorithm (the autofocus criterion calculation) by achieving a speedup of 8.9x over a sequential implementation on a state-of-the-art general-purpose processor of a later silicon technology generation and operating at a 2.7x higher clock speed. On the other case study, a highly memory-intensive algorithm (fast factorized backprojection), the Epiphany architecture shows a speedup of 4.25x. For embedded signal processing, low power dissipation is equally important as computational performance. In our case studies, the Epiphany implementations of the two algorithms are, respectively, 78x and 38x more energy efficient. © 2013 IEEE

  • 76.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Åhlander, Anders
    Saab AB, Gothenburg, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Real-time Radar Signal Processing on Massively Parallel Processor Arrays2013In: Conference Record of The Forty-Seventh Asilomar Conference on Signals, Systems & Computers: November 3–6, 2013 Pacific Grove, California / [ed] Michael B. Matthews, Piscataway, NJ: IEEE Signal Processing Society, 2013, p. 1810-1814Conference paper (Refereed)
    Abstract [en]

    The next generation radar systems have high performance demands on the signal processing chain. Among these are advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in realtime. Massively Parallel Processor Arrays (MPPAs) are gaining attention to cope with the computational requirements of complex radar signal processing by exploiting the massive parallelism inherent in the algorithms in an energy efficient manner.

    In this paper, we evaluate two such massively parallel architectures, namely, Ambric and Epiphany, by implementing a significantly large case study of autofocus criterion calculation, which is a key component in future synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance, energy efficiency, and programmability. ©2013 IEEE.

  • 77.
    Wickström, Nicholas
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Larsson, Magnus
    Mecel AB, Åmål, Sweden.
    Taveniku, Mikael
    Chalmers University of Technology, Göteborg, Sweden.
    Linde, Arne
    Chalmers University of Technology, Göteborg, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Chalmers University of Technology, Göteborg, Sweden.
    Neural Virtual Sensors — Estimation of Combustion Quality in SI Engines using the Spark Plug1998In: ICANN 98: Proceedings of the 8th International Conference on Artificial Neural Networks, Skövde, Sweden, 2-4 September 1998 / [ed] Lars Niklasson, Mikael Bodén, Tom Ziemke, London: Springer , 1998, p. 215-220Conference paper (Refereed)
    Abstract [en]

    We propose two virtual sensors which estimate the location of the pressure peak and the air-fuel ratio from measurements of the ionization current across the spark plug gap.

    The location of pressure peak virtual sensor produces estimates on a cycle-by-cycle basis for each of the cylinders. These estimates are twice as good as estimates obtained from a linear model.

    The air-fuel ratio virtual sensor uses the universal exhaust gas oxygen sensor as reference; it produces estimates that are ten times better than estimates obtained from a linear model.

  • 78.
    Wickström, Nicholas
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Taveniku, Mikael
    Chalmers.
    Linde, Arne
    Chalmers.
    Larsson, Magnus
    Mecel AB.
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Estimating pressure peak position and air-fuel ratio using the ionization current and artificial neural networks1997In: IEEE Conference on Intelligent Transportation Systems: proceedings, Boston Park Plaza Hotel, Boston, Massachusetts, November 9-12, 1997, Piscataway, N.J.: IEEE , 1997, p. 927-977Conference paper (Other academic)
    Abstract [en]

    We propose two artificial neural network models which use the ionization current for estimation of the position of the pressure peak and the air-fuel ratio. The pressure peak position model produces estimates on a cycle-by-cycle basis for each of the cylinders. These estimates are twice as good as estimates obtained from a linear model. The air-fuel ratio model uses the universal exhaust gas oxygen sensor as reference; it produces estimates that are ten times better than estimates obtained fi om a linear model.

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    FULLTEXT01
  • 79.
    Zain-ul-Abdin,
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Compiling Stream-Language Applications to a Reconfigurable Array Processor2005In: ERSA'05: proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA, June 27-30, 2005 / [ed] Toomas P. Plaks and R. DeMara, Las Vegas: CSREA Press, 2005, p. 274-275Conference paper (Refereed)
  • 80.
    Zain-ul-Abdin,
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Specifying Run-time Reconfiguration in Processor Arrays using High-level language2010In: WRC 2010: 4th HiPEAC Workshop on Reconfigurable Computing, Pisa, 2010, p. 1-10Conference paper (Refereed)
    Abstract [en]

    The adoption of run-time reconfigurable parallel architectures for high-performance embedded systems is constrained by the lackof a unified programming model which can express both parallelism and reconfigurability. We propose to program an emerging class of reconfigurable processor arrays by using the programming model of occam-pi and describe how the extensions of channel direction specifiers, mobile data, dynamic process invocation, and process placement attributes can be used to express run-time reconfiguration in occam-pi. We present implementations of DCT algorithm to demonstrate the applicability of occam-pi to express reconfigurability. We concluded that occam-pi appears to be a suitable programming model for programming run-time reconfigurable processor arrays.

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  • 81.
    Zain-ul-Abdin,
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Åhlander, Anders
    Business Area Electronic Defence Systems, Saab AB, Gothenburg, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Programming Real-time Autofocus on a Massively Parallel Reconfigurable Architecture using Occam-pi2011In: Proceedings of the 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM'2011), Los Alamitos, Calif.: IEEE Computer Society, 2011, p. 194-201Conference paper (Refereed)
    Abstract [en]

    Recently we proposed occam-pi as a high-level language for programming massively parallel reconfigurable architectures. The design of occam-pi incorporates ideas from CSP and pi-calculus to facilitate expressing parallelism and reconfigurability. The feasability of this approach was illustratedby building three occam-pi implementations of DCT executing on an Ambric. However, because DCT is a simple and well studied algorithm it remained uncertain whether occam-pi would also be effective for programming novel, more complex algorithms.

    In this paper, we demonstrate the applicability of occam-pi for expressing various degrees of parallelism by implementinga significantly large case-study of focus criterion calculation inan autofocus algorithm on the Ambric architecture. Autofocus is a key component of synthetic aperture radar systems. Two implementations of focus criterion calculation were developedand evaluated on the basis of performance. The comparison of the performance results with a single threaded software implementation of the same algorithm show that the throughput of the two implementations are 11x and 23x higher than the sequential implementation despite a much lower (9x) clock frequency. The two designs are, respectively, 29x and 40x moreenergy efficient.

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    fulltext
  • 82.
    Åhlander, Anders
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Hellsten, H.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Lind, K.
    Saab Microwave Systems, Gothenburg, Sweden.
    Lindgren, J.
    Saab Microwave Systems, Gothenburg, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Architectural challenges in memory-intensive, real-time image forming2007In: International Conference on Parallel Processing, 2007. ICPP 2007 / [ed] Li Jiandong, IEEE Press, 2007, p. 35-45Conference paper (Refereed)
    Abstract [en]

    The real-time image forming in future, high-end synthetic aperture radar systems is an example of an application that puts new demands on computer architectures. The initial question is whether it is at all possible to meet the demands with state-of-the-art technology or foreseeable new technology. It is therefore crucial to understand the computational flow, with its associated memory, bandwidth and processing demands. In this paper we analyse the application in order to, primarily, understand the algorithms and identify the challenges they present on a basic architectural level. The processing in the radar system is characterized by working on huge data sets, having complex memory access patterns, and doing real-time compensations for flight path errors. We propose algorithm solutions and execution schemes in interplay with a two-level (coarse-grain/fine-grain) system parallelization approach, and we provide approximate models on which the demands are quantified. In particular, we consider the choice of method for the performance-intensive data interpolations. This choice presents a trade-off problem between computational performance and size of working memory. The results of this "upstream" study will serve as a basis for further, more detailed architecture studies.

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    FULLTEXT01
  • 83.
    Åhlander, Anders
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Taveniku, Mikael
    Department of Computer Engineering, Chalmers University of Technology, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Department of Computer Engineering, Chalmers University of Technology, Sweden.
    A multiple SIMD approach to radar signal processing1996In: 1996 IEEE TENCON: Digital signal processing applications : proceedings : The University of Western Australia, Perth, Western Australia, 26-29 November 1996, Vol. 2 / [ed] Roberto Togneri, Piscataway, NJ: IEEE Press, 1996, p. 852-857Conference paper (Other academic)
    Abstract [en]

    Next generation radar systems, with phase-controlled array antennas, will have to process data that is many times larger than in current systems. This requires an enormous computing power. Even in a relatively small airborne radar system, with hard size and power consumption constraints, a sustained computing power of 40 GOPS (or 40 GFLOPS, if floating point calculations are used) will be needed to perform only the subset of the calculations known as the space-time adaptive processing, STAP Consequently, there is a need for new parallel computing modules, as well as new overall system architectures and application development environments. In this paper, a modular architecture with highly parallel SIMD-modules is presented as a promising solution, capable of handling STAP. A version of the architecture, equipped with bit-serial floating point PEs, is described and evaluated. Implementation technology aspects are discussed.

  • 84.
    Åhlander, Anders
    et al.
    Halmstad University, School of Information Technology.
    Taveniku, Mikael
    Halmstad University, School of Information Technology. Chalmers University of Technology, Gothenburg, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology. Chalmers University of Technology, Gothenburg, Sweden.
    Multiple SIMD approach to radar signal processing1997In: Proceedings of Digital Processing Applications (TENCON '96): vol. 2, Piscataway, NJ: IEEE, 1997, no 1336, p. 852-857Conference paper (Refereed)
    Abstract [en]

    Next generation radar systems, with phase-controlled array antennas, will have to process data that is many times larger than in current systems. This requires an enormous computing power. Even in a relatively small airborne radar system, with hard size and power consumption constraints, a sustained computing power of 40 GOPS (or 40 GFLOPS, if floating point calculations are used) will be needed to perform only the subset of the calculations known as the space-time adaptive processing, STAP. Consequently, there is a need for new parallel computing modules, as well as new overall system architectures and application development environments. In this paper, a modular architecture with highly parallel SIMD-modules is presented as a promising solution, capable of handling STAP. A version of the architecture, equipped with bit-serial floating point PEs, is described and evaluated. Implementation technology aspects are discussed.

  • 85.
    Åhlander, Anders
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Åström, Anders
    Airborne Radar Division, Ericsson Microwave Systems AB, Mölndal, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Taveniku, Mikael
    XCube Communication, Westford, MA, USA.
    Meeting Engineer Efficiency Requirements in Highly Parallel Signal Processing by Using Platforms2005In: Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems: November 14-16, 2005, Phoenix, AZ, USA / [ed] S. Q. Zheng, Anaheim: ACTA Press, 2005, p. 693-700Conference paper (Other (popular science, discussion, etc.))
    Abstract [en]

    One of the driving forces behind the development of new, highly parallel architectures is the need for embedded high-performance computing. The development of advanced applications on such architectures is, however, potentially connected to high costs. Cost-effective devel opment requires tools and processes that provide engineer efficiency, in this case tools and processes that help the developer master the application complexity. Related to engineer efficiency are the important concepts of system sustainability and flexibility. To address these issues, a platform approach can be taken. The platform should offer an understandable and stable development model, and at the same time give the possibility to take advantage of the rapid technology development, including the use of new parallel architectures. Thus it must support multiple hard ware targets, and the development model should decouple application development from mapping aspects. Two radar signal processing examples, one compute-intensive STAP and one data-intensive SAR, are used to illustrate the need. The GEPARD platform is presented as an example of our approach, and we argue that the described platform is a good fit for advanced signal processing development, facilitating the desired engineer efficiency, sustainability, and flexibility.

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