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  • 451.
    Zhang, Yan
    et al.
    Department of Informatics, University of Oslo, Oslo, Norway.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Li, Minqiang
    Department of Information Management and Management Science, Tianjin University, Tianjin, China.
    Guest editorial special issue on industrial IoT systems and applications2017In: IEEE Systems Journal, ISSN 1932-8184, E-ISSN 1937-9234, Vol. 11, no 3, p. 1337-1339, article id 8052330Article in journal (Other academic)
  • 452.
    Zhang, Yan
    et al.
    School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore, Singapore.
    Jonsson, MagnusHalmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).Li, MinqiangDepartment of Information Management and Management Science, College of Management and Economics, Tianjin University, Tianjin Shi, China.
    Special Issue on Industrial IoT Systems and Applications2017Collection (editor) (Refereed)
  • 453.
    Zheyuan, Liu
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Evaluation of platoon Application Enabled by Contemporary ETSI ITS-G5 Standards2015Independent thesis Advanced level (degree of Master (Two Years)), 80 credits / 120 HE creditsStudent thesis
  • 454.
    Zhuang, Weihua
    et al.
    University of Waterloo, Ontario, Canada.
    Jamalipour, Abbas
    University of Sydney, Sydney, New South Wales, Australia.
    Bai, Fan
    Carnegie Mellon University, Pittsburgh, Pennsylvania, USA.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Emerging Technologies, Applications, and Standardizations for Connecting Vehicles: [From the Guest Editors]2015In: IEEE Vehicular Technology Magazine, ISSN 1556-6072, E-ISSN 1556-6080, Vol. 10, no 4, p. 33-35Article in journal (Refereed)
    Abstract [en]

    The articles in this special section focus on the state of the art in the emerging technology for vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communications, the latest development in standardizations and regulations, and potential services and applications for vehicles on roads. © Copyright 2015 IEEE

  • 455.
    Zhuang, Weihua
    et al.
    Department of Electrical and Computer Engineering, University of Waterloo, ON, Canada.
    Jamalipour, Abbas
    University of Sydney, Sidney, Australia.
    Bai, Fan
    Caign, Universitarnegie Mellon University, University of Illinois at Urbana-Champy of Southern California, United States.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Emerging Technologies, Applications, and Standardizations for Connecting Vehicles (Part II)2017In: IEEE Vehicular Technology Magazine, ISSN 1556-6072, E-ISSN 1556-6080, Vol. 12, no 2, p. 23-25Article in journal (Other (popular science, discussion, etc.))
  • 456.
    Åhlander, Anders
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Efficient parallell architectures for future radar signal processing2007Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The processing demands on future embedded radar signal processors may stretch to several trillions of floating-point operations per second (TFLOPS). This is an increase of two to three orders of magnitude realtive to the requirements of today. Still, the tight size and power constraints are unchanged. To meet this, new, highly parallel computer systems are needed. The systems should efficiently deliver very high performance as well as being general enough. Another challenge for future signal processors is the requirement for having huge working memories that are accessed in complicated patterns.

    This thesis analyses the challenges of two classes of radar signal processing applications, namely Space-Time Adaptive Processing (STAP), which represents performance-intensive applications, and Synthetic Aperture Radar (SAR) processing, which represents memory-intensive applications. In addition to the actual performance and memory aspects of the applications, the desire for low-effort application development and maintenance is taken into consideration.

    A multiple SIMD architecture is proposed for the STAP calculations. This architecture gives a combination of the high computational density in the SIMD processing modules with the overall flexibility provided on the system level. An embedded signal processing system based on the architecture is shown to be capable of TFLOPS class performance using standard CMOS VLSI technology available in the year 2001. The system is, for the given application domain, considered to have the same generality as commercial off-the-shelf (COTS) hardware, but has several years of time lead over COTS with regard to the computational performance.

    The studied SAR processing is characterized by operating on huge data sets and having varying, non-linear data access paths. For this, algorithm solutions and execution schemes in inerplay with a system parallelization approach are proposed. It is shown that it is possible to obtain efficient memory accesses, despite the omplicated memory access patterns. It is also shown that the computational burden from complex interpolation kernels can be reduced through extensive calculation reuse.

    Efficient engineering of complex applications in this context is discussed. The use of semi-transparent, platform-based development is demonstrated for STAP and SAR, and advocated for obtaining high engineering defficiency and long system sustainability, as well as high performance efficiency.

    The overall conclusion drawn from this work is that a solid knowledge of the application domain and its future requirements, in combination with an understanding of its interaction with computational architectures, potentially enables several years of lead time in the realization of new, advanced signal prodcessing products. The important requirements on programmability and sustainability must also be taken into account in order to achieve a viable signal processing solution.

  • 457.
    Åhlander, Anders
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Hellsten, H.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Lind, K.
    Saab Microwave Systems, Gothenburg, Sweden.
    Lindgren, J.
    Saab Microwave Systems, Gothenburg, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Architectural challenges in memory-intensive, real-time image forming2007In: International Conference on Parallel Processing, 2007. ICPP 2007 / [ed] Li Jiandong, IEEE Press, 2007, p. 35-45Conference paper (Refereed)
    Abstract [en]

    The real-time image forming in future, high-end synthetic aperture radar systems is an example of an application that puts new demands on computer architectures. The initial question is whether it is at all possible to meet the demands with state-of-the-art technology or foreseeable new technology. It is therefore crucial to understand the computational flow, with its associated memory, bandwidth and processing demands. In this paper we analyse the application in order to, primarily, understand the algorithms and identify the challenges they present on a basic architectural level. The processing in the radar system is characterized by working on huge data sets, having complex memory access patterns, and doing real-time compensations for flight path errors. We propose algorithm solutions and execution schemes in interplay with a two-level (coarse-grain/fine-grain) system parallelization approach, and we provide approximate models on which the demands are quantified. In particular, we consider the choice of method for the performance-intensive data interpolations. This choice presents a trade-off problem between computational performance and size of working memory. The results of this "upstream" study will serve as a basis for further, more detailed architecture studies.

  • 458.
    Åhlander, Anders
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Åström, Anders
    Airborne Radar Division, Ericsson Microwave Systems AB, Mölndal, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Taveniku, Mikael
    XCube Communication, Westford, MA, USA.
    Meeting Engineer Efficiency Requirements in Highly Parallel Signal Processing by Using Platforms2005In: Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems: November 14-16, 2005, Phoenix, AZ, USA / [ed] S. Q. Zheng, Anaheim: ACTA Press, 2005, p. 693-700Conference paper (Other (popular science, discussion, etc.))
    Abstract [en]

    One of the driving forces behind the development of new, highly parallel architectures is the need for embedded high-performance computing. The development of advanced applications on such architectures is, however, potentially connected to high costs. Cost-effective devel opment requires tools and processes that provide engineer efficiency, in this case tools and processes that help the developer master the application complexity. Related to engineer efficiency are the important concepts of system sustainability and flexibility. To address these issues, a platform approach can be taken. The platform should offer an understandable and stable development model, and at the same time give the possibility to take advantage of the rapid technology development, including the use of new parallel architectures. Thus it must support multiple hard ware targets, and the development model should decouple application development from mapping aspects. Two radar signal processing examples, one compute-intensive STAP and one data-intensive SAR, are used to illustrate the need. The GEPARD platform is presented as an example of our approach, and we argue that the described platform is a good fit for advanced signal processing development, facilitating the desired engineer efficiency, sustainability, and flexibility.

78910 451 - 458 of 458
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