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  • 401.
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Workshop Report: Wireless Vehicular Communications [Society News]2013In: IEEE Vehicular Technology Magazine, ISSN 1556-6072, E-ISSN 1556-6080, Vol. 8, no 4, p. 100-104p. 100-104Article in journal (Other academic)
  • 402.
    Uhlemann, Elisabeth
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Rasmussen, Lars K.
    Inst. for Telecommunications Research, University of South Australia, Australia.
    Brännström, Fredrik
    Dept. of Signals and Systems, Chalmers University of Technology, Göteborg.
    Puncturing strategies for incremental redundancy schemes using rate compatible systematic serially concatenated codes2006In: International Symposium on Turbo Codes & Related Topics, 2006, International Symposium on Turbo Codes & Related Topics , 2006, p. 6-Conference paper (Refereed)
    Abstract [en]

    A rate compatible puncturing strategy intended for incremental redundancy retransmission schemes is derived. In particular, systematic serially concatenated codes with two or more component codes are considered, although the method is applicable to any type of concatenated code. Extrinsic information transfer charts are used to select a puncturing strategy such that the signal-to-noise ratio required to reach a target bit error rate is minimized.

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  • 403.
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Programming of Coarse-Grained Reconfigurable Architectures2011Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Coarse-grained reconfigurable architectures, which offer massive parallelism coupled with the capability of undergoing run-time reconfiguration, are gaining attention in order to meet not only the increased computational demands of high-performance embedded systems, but also to fulfill the need of adaptability to functional requirements of the application. This thesis focuses on the programming aspects of such coarse-grained reconfigurable computing devices, including the relevant computation models that are capable of exposing different kinds of parallelism inherent in the application and the ability of these models to capture the adaptability requirements of the application. The thesis suggests the occam-pi language for programming of a broad class of coarse-grained reconfigurable architectures as an intermediate language; we call it intermediate, since we believe that the applicationprogramming is best done in a high-level domain-specific language. The salient properties of the occam-pi language are explicit concurrency with built-in mechanisms for interprocessorcommunication, provision for expressing dynamic parallelism, support for the expression of dynamic reconfigurations, and placement attributes. To evaluate the programming approach, a compiler framework was extended to support the language extensions in the occam-pi language, and backends were developed to target two different coarse-grained reconfigurable architectures. XPP and Ambric. The results on XPP reveal that the occam-pi based implementations produce comparable throughput to those of NML programs, while programming at a much higher level of abstraction than that of NML. Similarly the two occam-pi implementations of autofocus criterion calculation targeted to the Ambric platform outperform the CPU implementation by factors of 11-23. Thus, the results of the implemented case-studies suggest that the occam-pi language based approach simplifies the development of applications employing run-time reconfigurable devices without compromising the performance benefits.

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  • 404.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Gebrewahid, Essayas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Managing Dynamic Reconfiguration for Fault-tolerance on a Manycore Architecture2012In: Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012, New York, USA: IEEE Computer Society, 2012, p. 312-319, article id 6270657Conference paper (Refereed)
    Abstract [en]

    With the advent of manycore architectures comprising hundreds of processing elements, fault management has become a major challenge. We present an approach that uses the occam-pi language to manage the fault recovery mechanism on a new manycore architecture, the Platform 2012 (P2012). The approach is made possible by extending our previously developed compiler framework to compile occam-pi implementations to the P2012 architecture. We describe the techniques used to translate the salient features of the occam-pi language to the native programming model of the P2012 architecture. We demonstrate the applicability of the approach by an experimental case study, in which the DCT algorithm is implemented on a set of four processing elements. During run-time, some of the tasks are then relocated from assumed faulty processing elements to the faultless ones by means of dynamic reconfiguration of the hardware. The working of the demonstrator and the simulation results illustrate not only the feasibility of the approach but also how the use of higher-level abstractions simplifies the fault handling. © 2012 IEEE.

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  • 405.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Mingkun, Yang
    Uppsala University, Uppsala, Sweden.
    A Radar Signal Processing Case Study for Dataflow Programming of Manycores2017In: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115, Vol. 87, no 1, p. 49-62Article in journal (Refereed)
    Abstract [en]

    The successful realization of next generation radar systems have high performance demands on the signal processing chain. Among these are advanced Active Electronically Scanned Array (AESA) radars in which complex calculations are to be performed on huge sets of data in real-time. Manycore architectures are designed to provide flexibility and high performance essential for such streaming applications. This paper deals with the implementation of compute-intensive parts of AESA radar signal processing chain in a high-level dataflow language; CAL. We evaluate the approach by targeting a commercial manycore architecture, Epiphany, and present our findings in terms of performance and productivity gains achieved in this case study. The comparison of the performance results with the reference sequential implementations executing on a state-of-the-art embedded processor show that we are able to achieve a speedup of 1.6x to 4.4x by using only 10 cores of Epiphany. © Springer Science+Business Media New York 2015

  • 406.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). TeleSehat Private Limited, Islamabad, Pakistan.
    Shafique, Muhammad
    Karlsruhe Institute of Technology, Karlsruhe, Germany.
    Qadir, Muhammad Abdul
    Mohammad Ali Jinnah University, Islamabad, Pakistan.
    Evaluating Video Codecs for Telemedicine Under Very-Low Bitrates2015In: 2015 8th International Congress on Image and Signal Processing (CISP) / [ed] Wang L.,Lin S.,Tao Z.,Zeng B.,Hui X.,Shao L.,Liang J., Piscataway, NJ: IEEE, 2015, p. 98-103, article id 7407857Conference paper (Refereed)
    Abstract [en]

    Telemedicine is drawing greater attention to improve the health care delivery. Video coding being an integral part of any real-time telemedicine system is used to deliver diagnostic video stream to remote physician. Realizing a video coding system customized for telemedicine, using the available technologies poses several challenges. In this paper, we have analyzed state-of-the-art video codecs for adoption in telemedicine customized video conferencing system under low-bandwidth and low-computational scenarios. The experimental results for the selected video codec implementations for medical videos reveal that the HEVC encoder achieves equivalent objective video quality when using approx. 60% bit rate on average. However, the gain in coding efficiency is at the expense of increased computational complexity, which could be dealt with by incorporating adaptive interpolation and selective quality enhancement techniques to achieve real-time performance. © 2015 IEEE.

  • 407.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing2016In: ACM Transactions on Reconfigurable Technology and Systems, ISSN 1936-7406, E-ISSN 1936-7414, Vol. 9, no 4, article id 24Article in journal (Refereed)
    Abstract [en]

    The future trend in microprocessors for the more advanced embedded systems is focusing on massively parallel reconfigurable architectures, consisting of heterogeneous ensembles of hundreds of processing elements communicating over a reconfigurable interconnection network. However, the mastering of low-level micro-architectural details involved in programming of such massively parallel platforms becomes too cumbersome, which limits their adoption in many applications. Thus there is a dire need of an approach to produce high-performance scalable implementations that harness the computational resources of the emerging reconfigurable platforms.This paper addresses the grand challenge of accessibility of these diverse reconfigurable platforms by suggesting the use of a high-level language, occam-pi, and developing a complete design flow for building, compiling, and generating machine code for heterogeneous coarse-grained hardware. We have evaluated the approach by implementing complex industrial case studies and three common signal processing algorithms. The results of the implemented case-studies suggest that the occam-pi language based approach, because of its well-defined semantics for expressing concurrency and reconfigurability, simplifies the development of applications employing run-time reconfigurable devices. The associated compiler framework ensures portability as well as the performance benefits across heterogeneous platforms.

  • 408.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Study of Design Efficiency with a High-Level Language for FPGAs2007In: Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Abstracts and CD-ROM, Piscataway, N.J.: IEEE Press, 2007, p. 1-7Conference paper (Refereed)
    Abstract [en]

    Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used for mapping computations to such architectures still require the knowledge about architectural details of the target device to extract efficiency. A study of the Mobius language and tools is presented in this paper, with a focus on generated hardware performance. A number of streaming and memory-intensive applications have been developed and the results have been compared with the corresponding implementations in VHDL and a behavioral hardware description language. Based upon experimental evidences, it is concluded that Mobius, a minimal parallel processing language targeted for reconfigurable architectures, enhances productivity in terms of design time and code maintainability without considerably compromising performance and resources.

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  • 409.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    An Evaluation of High-Performance Embedded Processing on MPPAs2013In: Proceedings: 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2013, Los Alamitos, California: IEEE Computer Society, 2013, p. 235-235, article id 6546032Conference paper (Refereed)
    Abstract [en]

    Embedded signal processing is facing the challenges of increased performance as well as to achieve energy efficiency. Massively parallel processor arrays (MPPAs) consisting of tens or hundreds of processing cores offer the possibility of meeting the growing performance demand in an energy efficient way by exploiting parallelism instead of scaling the clock frequency of a single powerful processor.

    In this paper, we evaluate two variants of MPPAs by implementing a significantly large case study, namely an autofocus criterion calculation, which is a key component in modern synthetic aperture radar systems. The implementation results from the two target architectures are compared on the basis of utilized resources, performance, and energy efficiency. The Ambric implementations demonstrate the usefulness of occam-pi based high-level language approach in utilizing hundreds of processors, whereas the Epiphany implementation reveals that energy-efficiency can be improved even further by a factors of 2-3 with respect to the Ambric implementations and can be achieved at high clock speeds. © 2013 IEEE.

  • 410.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Occam-pi as a High-level Language for Coarse-Grained Reconfigurable Architectures2011In: IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, Washington, USA: IEEE Computer Society, 2011, p. 236-243Conference paper (Refereed)
    Abstract [en]

    Recently we proposed occam-pi as a high-levellanguage for programming coarse grained reconfigurable architectures. The constructs of occam-pi combine ideas from CSPand pi-calculus to facilitate expressing parallelism, communication, and reconfigurability. The feasability of this approachwas illustrated by developing a compiler framework to compile occam-pi implementations to the Ambric architecture. In this paper, we demonstrate the applicability of occam-pif or programing an array of functional units, eXtreme ProcessingPlatform (XPP). This is made possible by extending the compilerframework to target the XPP architecture, including automatic floating to fixed-point conversion. Different implementations of a FIR filter and a DCT algorithm were developed and evaluated on the basis of performance and resource consumption. The reported results reveal that the approach of using occam-pito program the category of coarse grained reconfigurable architectures appears to be promising. The resulting implementations are generally much superior to those programmed in C and comparable to those hand-coded in the low-level native language NML.

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  • 411.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Occam-pi for Programming of Massively Parallel Reconfigurable Architectures2012In: International Journal of Reconfigurable Computing, ISSN 1687-7195, E-ISSN 1687-7209, Vol. 2012, article id 504815Article in journal (Refereed)
    Abstract [en]

    Massively parallel reconfigurable architectures, which offer massive parallelism coupled with the capability of undergoing run-time reconfiguration, are gaining attention in order to meet the increased computational demands of high-performance embedded systems. We propose that the occam-pi language is used for programming of the category of massively parallel reconfigurable architectures. The salient properties of the occam-pi language are explicit concurrency with built-in mechanisms for interprocessor communication, provision for expressing dynamic parallelism, support for the expression of dynamic reconfigurations, and placement attributes. To evaluate the programming approach, a compiler framework was extended to support the language extensions in the occam-pi language and a backend was developed to target the Ambric array of processors. We present two case-studies; DCT implementation exploiting the reconfigurability feature of occam-pi and a significantly large autofocus criterion calculation based on the dynamic parallelism capability of the occam-pi language. The results of the implemented case studies suggest that the occam-pi -language-based approach simplifies the development of applications employing run-time reconfigurable devices without compromising the performance benefits. Copyright © 2012 Zain-ul-Abdin and Bertil Svensson.

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  • 412.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Synthetic-Aperture Radar Processing on a Manycore Architecture2012Conference paper (Refereed)
    Abstract [en]

    Synthetic-Aperture Radar (SAR) systems that are used to create high-resolution radar images from low-resolution aperture data require high computational performance. Manycore architectures are emerging to overcome the computational requirements of the complex radar signal processing.

    In this paper, we evaluate a manycore architecture namely Epiphany by implementing two significantly large case studies of fast factorized back-projection and autofocus criterion calculation, which are key components in modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of utilized resources and performance. The Epiphany implementations demonstrate the usefulness of the architecture for the streaming algorithm (autofocus criterion calculation) by achieving speedup of 8.9x with respect to the sequential implementation on Intel Core i7 processor while operating at a lower clock speed. On the other hand, for the memory-intensive algorithm (fast factorized back-projection), the Epiphany architecture shows moderate speedup in the order of 4.25x. The Epiphany implementations of the two algorithms are, respectively, 38x and 78x more energy-efficient.

  • 413.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Towards Teaching Embedded Parallel Computing: An Analytical Approach2015In: Workshop on Computer Architecture Education, WCAE 2015, 2015Conference paper (Refereed)
    Abstract [en]

    Embedded electronic systems are finding increased applications in our daily life. In order to meet the application demands in embedded systems, parallel computing is used. This paper emphasizes teaching of the specific issues of parallel computing that are critical to embedded systems. We propose an analytical approach to deliver declarative and functioning knowledge for learning in the field of computer science and engineering with a special focus on Embedded Parallel Computing (EPC). We describe the teaching of a course with a focus on how parallel computing can be used to enhance performance and improve energy efficiency of embedded systems. The teaching methods include interactive lectures with web-based course literature, seminars, and lab exercises and home-assigned practical tasks. Further, the course is intended to give a general insight into current research and development in regard to parallel architectures and computation models. Since the course is an advanced level course, the students are expected to have a basic knowledge about the fundamentals of computer architecture and their common programming methodologies. The course puts emphasis on hands-on experience with embedded parallel computing. Therefore it includes an extensive laboratory and project part, in which a state of the art manycore embedded computing system is used. We believe that undertaking these methods in succession will prepare the students for both research as well as professional career. © 2015 ACM.

  • 414.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Yang, Mingkun
    Uppsala University, Uppsala, Sweden.
    Dataflow Programming of Real-time Radar Signal Processing on Manycores2014In: 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP), Piscataway, NJ: IEEE Press, 2014, p. 15-19Conference paper (Refereed)
    Abstract [en]

    Real-time performance is critical for the successful realization of next generation radar systems. Among these are advanced Active Electronically Scanned Array (AESA) radars in which complex calculations are to be performed on huge sets of data in real-time. Manycore architectures are designed to provide flexibility and high performance essential for such streaming applications.

    This paper deals with the implementation of compute-intensive parts of AESA radar signal processing chain in a high-level dataflow language; CAL. We evaluate the approach by targeting a commercial manycore architecture, Epiphany, and present our preliminary findings in terms of performance and productivity gains achieved in this case study. © 2014 IEEE.

  • 415.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Åhlander, Anders
    Saab AB, Gothenburg, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Energy-Efficient Synthetic-Aperture Radar Processing on a Manycore Architecture2013In: Proceedings: International Conference on Parallel Processing : The 42nd Annual Conference : ICPP 2013 : 1-4 October 2013 : Lyon, France / [ed] Randall Bilof, Piscataway, NJ: IEEE conference proceedings, 2013, p. 330-338, article id 6687366Conference paper (Refereed)
    Abstract [en]

    The next generation radar systems have high performance demands on the signal processing chain. Examples include the advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in realtime. Manycore architectures are gaining attention as a means to overcome the computational requirements of the complex radar signal processing by exploiting massive parallelism inherent in the algorithms in an energy efficient manner.

    In this paper, we evaluate a manycore architecture, namely a 16-core Epiphany processor, by implementing two significantly large case studies, viz. an autofocus criterion calculation and the fast factorized back-projection algorithm, both key componentsin modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance and programmability. One of the Epiphany implementations demonstrates the usefulness of the architecture for the streaming based algorithm (the autofocus criterion calculation) by achieving a speedup of 8.9x over a sequential implementation on a state-of-the-art general-purpose processor of a later silicon technology generation and operating at a 2.7x higher clock speed. On the other case study, a highly memory-intensive algorithm (fast factorized backprojection), the Epiphany architecture shows a speedup of 4.25x. For embedded signal processing, low power dissipation is equally important as computational performance. In our case studies, the Epiphany implementations of the two algorithms are, respectively, 78x and 38x more energy efficient. © 2013 IEEE

  • 416.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Åhlander, Anders
    Saab AB, Gothenburg, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Real-time Radar Signal Processing on Massively Parallel Processor Arrays2013In: Conference Record of The Forty-Seventh Asilomar Conference on Signals, Systems & Computers: November 3–6, 2013 Pacific Grove, California / [ed] Michael B. Matthews, Piscataway, NJ: IEEE Signal Processing Society, 2013, p. 1810-1814Conference paper (Refereed)
    Abstract [en]

    The next generation radar systems have high performance demands on the signal processing chain. Among these are advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in realtime. Massively Parallel Processor Arrays (MPPAs) are gaining attention to cope with the computational requirements of complex radar signal processing by exploiting the massive parallelism inherent in the algorithms in an energy efficient manner.

    In this paper, we evaluate two such massively parallel architectures, namely, Ambric and Epiphany, by implementing a significantly large case study of autofocus criterion calculation, which is a key component in future synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance, energy efficiency, and programmability. ©2013 IEEE.

  • 417.
    Varshosaz, Mahsa
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Modeling and Model-Based Testing of Software Product Lines2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Software product line (SPL) engineering has become common practice for mass production and customization of variability intensive systems. A software product line comprises a family of software systems which share a managed core set of artifacts and also have a set of well-defined variabilities. The main idea in SPL engineering is to enable systematic reuse in different phases of software development to reduce cost and time to release.

    Model-Based Testing (MBT) is a technique that is widely used for quality assurance of software systems. In MBT, an abstract model, which captures the desired behavior of the system, is used to generate test cases. The test cases are executed against a real implementation of the system and the conformance between the implementation and the specification is checked by comparing the observed outputs with the ones prescribed by the model.

    Software product lines have been applied in a number of domains with mission critical systems. MBT is one of the techniques that has been used for analysis of such systems. As the number of products can be potentially large in an SPL, using conventional approaches for MBT of the products of an SPL individually can be very costly and time consuming. To tackle this problem, several approaches have been proposed in order to enable systematic reuse in different phases of the MBT process.

    An efficient modeling technique is the first step towards an efficient MBT technique for SPLs. So far, several formalisms have been proposed for modeling SPLs. In this thesis, we conduct a study on such modeling techniques, focusing on four fundamental formalisms, namely featured transition systems, modal transition systems, product line calculus of communicating systems, and 1- selecting modal transition systems. We compare the expressive power and the succinctness of these formalisms.

    Furthermore, we investigate adapting existing MBT methods for efficient testing of SPLs. As a part of this line of our research, we adapt the test case generation algorithm of one of the well-known black-box testing approaches, namely, Harmonized State Identification (HSI) method by exploiting the idea of delta-oriented programming. We apply the adapted test case generation algorithm to a case study taken from industry and the results show up to 50 percent reduction of time in test case generation by using the delta-oriented HSI method.

    In line with our research on investigating existing MBT techniques, we compare the relative efficiency and effectiveness of the test case generation algorithms of the well-known Input-Output Conformance (ioco) testing approach and the complete ioco which is another testing technique used for input output transition systems that guarantees fault coverage. The comparison is done using three case studies taken from the automotive and railway domains. The obtained results show that complete ioco is more efficient in detecting deep faults (i.e., the faults reached through longer traces) in large state spaces while ioco is more efficient in detecting shallow faults (i.e., the faults reached through shorter traces) in small state spaces.

    Moreover, we conduct a survey on sampling techniques, which have been proposed as a solution for handling the large number of products in analysis. In general, in product sampling a subset of products that collectively cover the behavior of the product line are selected. Performing tests on well selected sample set can reveal most of the faults in all products. We provide a classification for a catalog of studies on product sampling for software product lines. Additionally, we present a number of insights on the studied work as well as gaps for the future research.

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  • 418.
    Varshosaz, Mahsa
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Test Models and Algorithms for Model-Based Testing of Software Product Lines2017Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Software product line (SPL) engineering has become common practice for mass production and customization of software. A software product line comprises a family of software systems which share a managed core set of artifacts. There are also a set of well-defined variabilities between the products of a product line. The main idea in SPL engineering is to enable systematic reuse in different phases of software development to reduce cost and time to release.

    Model-Based Testing (MBT) is a technique that is widely used for checking the quality of software systems. In MBT, test cases are generated from an abstract model, which captures the desired behavior of the system. Then, the test cases are executed against a real implementation of the system and the compliance of the implementation to the specification is checked by comparing the observed outputs with the ones prescribed by the model.

    Software product lines have been applied in many domains in which sys- tems are mission critical and MBT is one of the techniques that is widely used for quality assurance of such systems. As the number of products can be potentially large in an SPL, using conventional approaches for MBT of the products of an SPL individually and as single systems can be very costly and time consuming. Hence, several approaches have been proposed in order to enable systematic reuse in different phases of the MBT process.

    An efficient modeling technique is the first step towards an efficient MBT technique for SPLs. There have been several formalisms proposed for modeling SPLs. In this thesis, we conduct a study on such modeling techniques, focusing on three fundamental formalisms, namely featured transition systems, modal transition systems, and product line calculus of communicating systems. We compare the expressive power and the succinctness of these formalisms.

    Furthermore, we investigate adapting existing MBT methods for efficient testing of SPLs. As a part of this line of our research, we adapt the test case generation algorithm of one of the well-known black-box testing approaches, namely, Harmonized State Identification (HSI) method by exploiting the idea of delta-oriented programming. We apply the adapted test case generation algorithm to a case study taken from industry and the results show up to 50 percent reduction of time in test case generation by using the delta-oriented HSI method.

    In line with our research on investigating existing MBT techniques, we compare the relative efficiency and effectiveness of the test case generation algorithms of the well-known Input-Output Conformance (ioco) testing approach and the complete ioco which is another testing technique used for input output transition systems that guarantees fault coverage. The comparison is done using three case studies taken from the automotive and railway domains. The obtained results show that complete ioco is more efficient in detecting deep faults (i.e., the faults reached through longer traces) in large state spaces while ioco is more efficient in detecting shallow faults (i.e., the faults reached through shorter traces) in small state spaces.

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  • 419.
    Varshosaz, Mahsa
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Al-Hajjaji, Mustafa
    Pure-Systems GmbH, Neustadt, Germany.
    Thüm, Thomas
    Technische Universität, Braunschweig, Braunschweig, Germany.
    Runge, Tobias
    Technische Universität, Braunschweig, Braunschweig, Germany.
    Mousavi, Mohammad Reza
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). University of Leicester, Leicester, United Kingdom.
    Schaefer, Ina
    Technische Universität, Braunschweig, Braunschweig, Germany.
    A classification of product sampling for software product lines2018In: SPLC '18 Proceedings of the 22nd International Systems and Software Product Line Conference - Volume 1 / [ed] Berger et al., New York, NY: Association for Computing Machinery (ACM), 2018, p. 1-13Conference paper (Refereed)
    Abstract [en]

    The analysis of software product lines is challenging due to the potentially large number of products, which grow exponentially in terms of the number of features. Product sampling is a technique used to avoid exhaustive testing, which is often infeasible. In this paper, we propose a classification for product sampling techniques and classify the existing literature accordingly. We distinguish the important characteristics of such approaches based on the information used for sampling, the kind of algorithm, and the achieved coverage criteria. Furthermore, we give an overview on existing tools and evaluations of product sampling techniques. We share our insights on the state-of-the-art of product sampling and discuss potential future work. © 2018 Association for Computing Machinery.

  • 420.
    Varshosaz, Mahsa
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Beohar, Harsh
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Mousavi, Mohammad Reza
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Basic Behavioral Models For Software Product Lines: Revisited2018In: Science of Computer Programming, ISSN 0167-6423, E-ISSN 1872-7964, Vol. 168, p. 171-185Article in journal (Refereed)
    Abstract [en]

    In Beohar et al. (2016) [9], we established an expressiveness hierarchy and studied the notions of refinement and testing for three fundamental behavioral models for software product lines. These models were featured transition systems, product line labeled transition systems, and modal transition systems. It turns out that our definition of product line labeled transition systems is more restrictive than the one introduced by Gruler, Leucker, and Scheidemann. Adopting the original and more liberal notion changes the expressiveness results, as we demonstrate in this paper. Namely, we show that the original notion of product line labeled transition systems and featured transition systems are equally expressive. As an additional result, we show that there are featured transition systems for which the size of the corresponding product line labeled transition system, resulting from any sound encoding, is exponentially larger than the size of the original model. Furthermore, we show that each product line labeled transition system can be encoded into a featured transition system, such that the size of featured transition system is linear in terms of the size of the corresponding model. To summarize, featured transition systems are equally expressive as, but exponentially more succinct than, product line labeled transition systems. © 2018 Elsevier B.V.

  • 421.
    Varshosaz, Mahsa
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Beohar, Harsh
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Mousavi, Mohammad Reza
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Delta-Oriented FSM-Based Testing2015In: Formal Methods and Software Engineering: 17th International Conference on Formal Engineering Methods, ICFEM 2015, Paris, France, November 3-5, 2015, Proceedings / [ed] Michael Butler, Sylvain Conchon & Fatiha Zaïdi, Cham: Springer, 2015, Vol. 9407, p. 366-381Conference paper (Refereed)
    Abstract [en]

    We use the concept of delta-oriented programming to organize FSM-based test models in an incremental structure. We then exploit incremental FSM-based testing to make efficient use of this high-level structure in generating test cases. We show how our approach can lead to more efficient test-case generation, both by analyzing the complexity of the test-case generation algorithm and by applying the technique to a case study. © Springer International Publishing Switzerland 2015

  • 422.
    Varshosaz, Mahsa
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Luthmann, Lars
    Technische Universität Darmstadt, Darmstadt, Germany.
    Mohr, Paul
    Technische Universität Darmstadt, Darmstadt, Germany.
    Lochau, Malte
    Technische Universität Darmstadt, Darmstadt, Germany.
    Mousavi, Mohammad Reza
    University of Leicester, Leicester, United Kingdom.
    Modal Transition System Encoding of Featured Transition Systems2019In: The Journal of logical and algebraic methods in programming, ISSN 2352-2208, E-ISSN 2352-2216, Vol. 106, p. 1-28Article in journal (Refereed)
    Abstract [en]

    Featured transition systems (FTSs) and modal transition systems (MTSs) are two of the most prominent and well-studied formalisms for modeling and analyzing behavioral variability as apparent in software product line engineering. On one hand, it is well-known that for finite behavior FTSs are strictly more expressive than MTSs, essentially due to the inability of MTSs to express logically constrained behavioral variability such as persistently exclusive behaviors. On the other hand, MTSs enjoy many desirable formal properties such as compositionality of semantic refinement and parallel composition. In order to finally consolidate the two formalisms for variability modeling, we establish a rigorous connection between FTSs and MTSs by means of an encoding of one FTS into an equivalent set of multiple MTSs. To this end, we split the structure of an FTS into several MTSs whenever it is necessary to denote exclusive choices that are not expressible in a single MTS. Moreover, extra care is taken when dealing with infinite behaviour: loops may have to be unrolled to accumulate FTS path constraints when encoding them into MTSs. We prove our encoding to be semanticpreserving (i.e., the resulting set of MTSs induces, up to bisimulation, the same set of derivable variants as their FTS counterpart) and to commute with modal refinement. We further give an algorithm to calculate a concise representation of a given FTS as a minimal set of MTSs. Finally, we present experimental results gained from applying a tool implementation of our approach to a collection of case studies.

  • 423.
    Varshosaz, Mahsa
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Mousavi, Mohammad Reza
    Department of Informatics, University of Leicester, Leicester, United Kingdom.
    Comparative Expressiveness of Product Line Calculus of Communicating Systems and 1-Selecting Modal Transition Systems2019In: SOFSEM 2019: Theory and Practice of Computer Science / [ed] Barbara Catania, Rastislav Královič, Jerzy Nawrocki & Giovanni Pighizzini, Cham: Springer, 2019, p. 490-503Conference paper (Refereed)
    Abstract [en]

    Product line calculus of communicating systems (PL-CCSs) is a process calculus proposed to model the behavior of software product lines. Modal transition systems (MTSs) are also used to model variability in behavioral models. MTSs are known to be strictly less expressive than PL-CCS. In this paper, we show that the extension of MTSs with hyper transitions by Fecher and Schmidt, called 1-selecting modal transition systems (1MTSs), closes this expressiveness gap. To this end, we propose a novel notion of refinement for 1MTSs that makes them more suitable for specifying variability for software product lines and prove its various essential properties. © Springer Nature Switzerland AG 2019

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  • 424.
    Vedder, Benjamin
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Testing Safety-Critical Systems using Fault Injection and Property-Based Testing2015Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Testing software-intensive systems can be challenging, especially when safety requirements are involved. Property-Based Testing (PBT) is a software testing technique where properties about software are specified and thousands of test cases with a wide range of inputs are automatically generated based on these properties. PBT does not formally prove that the software fulfils its specification, but it is an efficient way to identify deviations from the specification. Safety-critical systems that must be able to deal with faults, without causing damage or injuries, are often tested using Fault Injection (FI) at several abstraction levels. The purpose of FI is to inject faults into a system in order to exercise and evaluate fault handling mechanisms. The aim of this thesis is to investigate how knowledge and techniques from the areas of FI and PBT can be used together to test functional and safety requirements simultaneously.

    We have developed a FI tool named FaultCheck that enables PBT tools to use common FI-techniques directly on source code. In order to evaluate and demonstrate our approach, we have applied our tool FaultCheck together with the commercially available PBT tool QuickCheck on a simple and on a complex system. The simple system is the AUTOSAR End-to-End (E2E) library and the complex system is a quadcopter simulator that we developed ourselves. The quadcopter simulator is based on a hardware quadcopter platform that we also developed, and the fault models that we inject into the simulator using FaultCheck are derived from the hardware quadcopter platform. We were able to efficiently apply FaultCheck together with QuickCheck on both the E2E library and the quadcopter simulator, which gives us confidence that FI together with PBT can be used to test and evaluate a wide range of simple and complex safety-critical software.

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  • 425.
    Vedder, Benjamin
    et al.
    SP Electronics, SP Technical Research, Institute of Sweden, Borås, Sweden.
    Arts, Thomas
    Quviq AB, Göteborg, Sweden.
    Vinter, Jonny
    SP Electronics, SP Technical Research, Institute of Sweden, Borås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Combining Fault-Injection with Property-Based Testing2014In: ES4CPS: Workshop Proceedings of Engineering Simulations for Cyber Physical Systems, New York: ACM Press, 2014Conference paper (Refereed)
    Abstract [en]

    In this paper we present a methodology and a platform using Fault Injection (FI) and Property-Based Testing (PBT). PBT is a technique in which test cases are automatically generated from a specification of a system property. The generated test cases vary input stimuli as well as the sequence in which commands are executed. FI is used to accelerate the occurrences of faults in a system to exercise and evaluate fault handling mechanisms and e.g. calculate error detection coverage. By combining the two we have achieved a way of randomly injecting different faults at arbitrary moments in the execution sequence while checking whether certain properties still hold. We use the commercially available tool QuickCheck for generating the test cases and developed FaultCheck for FI. FaultCheck enables the user to utilize fault models, commonly used during FI, from PBT tools like QuickCheck. We demonstrate our method and tools on a simplified example of two Airbag systems that should meet safety requirements. We can easily find a safety violation in one of the examples, whereas by using the AUTOSAR E2E-library implementation, exhaustive testing cannot reveal any such safety violation. This demonstrates that our approach on testing can reveal certain safety violations in a cost-effective way. © 2014 ACM.

  • 426.
    Vedder, Benjamin
    et al.
    Department of Electronics, SP Technical Research Institute of Sweden, Borås, Sweden.
    Eriksson, Henrik
    Department of Electronics, SP Technical Research Institute of Sweden, Borås, Sweden.
    Skarin, Daniel
    Department of Electronics, SP Technical Research Institute of Sweden, Borås, Sweden.
    Vinter, Jonny
    Department of Electronics, SP Technical Research Institute of Sweden, Borås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Towards Collision Avoidance for Commodity Hardware Quadcopters with Ultrasound Localization2015In: 2015 International Conference on Unmanned Aircraft Systems (ICUAS), [S.l.]: IEEE, 2015, p. 193-203Conference paper (Refereed)
    Abstract [en]

    We present a quadcopter platform built with commodity hardware that is able to do localization in GNSS-denied areas and avoid collisions by using a novel easy-to-setup and inexpensive ultrasound-localization system. We address the challenge to accurately estimate the copter's position and not hit any obstacles, including other, moving, quadcopters. The quadcopters avoid collisions by placing contours that represent risk around static and dynamic objects and acting if the risk contours overlap with ones own comfort zone. Position and velocity information is communicated between the copters to make them aware of each other. The shape and size of the risk contours are continuously updated based on the relative speed and distance to the obstacles and the current estimated localization accuracy. Thus, the collision-avoidance system is autonomous and only interferes with human or machine control of the quadcopter if the situation is hazardous. In the development of this platform we used our own simulation system using fault-injection (sensor faults, communication faults) together with automatically-generated tests to identify problematic scenarios for which the localization and risk contour parameters had to be adjusted. In the end, we were able to run thousands of simulations without any collisions, giving us confidence that also many real quadcopters can manoeuvre collision free in space-constrained GNSS-denied areas. ©2015 IEEE.

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  • 427.
    Vedder, Benjamin
    et al.
    Department of Electronics, RISE Research Institutes of Sweden, Borås, Sweden.
    Svensson, Bo Joel
    Department of Electronics, RISE Research Institutes of Sweden, Borås, Sweden.
    Vinter, Jonny
    Department of Electronics, RISE Research Institutes of Sweden, Borås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Automated Testing of Ultrawideband Positioning for Autonomous Driving2020In: Journal of Robotics, ISSN 1687-9600, E-ISSN 1687-9619, Vol. 2020, article id 9345360Article in journal (Refereed)
    Abstract [en]

    Autonomous vehicles need accurate and dependable positioning, and these systems need to be tested extensively. We have evaluated positioning based on ultrawideband (UWB) ranging with our self-driving model car using a highly automated approach. Random drivable trajectories were generated, while the UWB position was compared against the Real-Time Kinematic Satellite Navigation (RTK-SN) positioning system which our model car also is equipped with. Fault injection was used to study the fault tolerance of the UWB positioning system. Addressed challenges are automatically generating test cases for real-time hardware, restoring the state between tests, and maintaining safety by preventing collisions. We were able to automatically generate and carry out hundreds of experiments on the model car in real time and rerun them consistently with and without fault injection enabled. Thereby, we demonstrate one novel approach to perform automated testing on complex real-time hardware. Copyright © 2020 Benjamin Vedder et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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  • 428.
    Vedder, Benjamin
    et al.
    RISE Research Institutes of Sweden, Gothenburg, Sweden.
    Vinter, Jonny
    RISE Research Institutes of Sweden, Gothenburg, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Accurate positioning of bicycles for improved safety2018In: 2018 IEEE International Conference on Consumer Electronics (ICCE) / [ed] Saraju P. Mohanty, Peter Corcoran & Hai (Helen) Li, Piscataway, NJ: IEEE, 2018Conference paper (Refereed)
    Abstract [en]

    Cyclists are not well protected in accidents with other road users, and there are few active safety systems available for bicycles. In this study we have evaluated the use of inexpensive Real-Time Kinematic Satellite Navigation (RTK-SN) receivers with multiple satellite constellations together with dead reckoning for accurate positioning of bicycles to enable active safety functions such as collision warnings. This is a continuation of previous work were we concluded that RTK-SN alone is not sufficient in moderately dense urban areas as buildings and other obstructions degrade the performance of RTK-SN significantly. In this work we have added odometry to the positioning system as well as extending RTK-SN with multiple satellite constellations to deal with situations where the view of the sky is poor and thus fewer satellites are in view. To verify the performance of the positioning system we have used Ultra-Wideband radios as an independent positioning system to compare against while testing during poor conditions for RTK-SN. We were able to verify that adding dead reckoning and multiple satellite constellations improves the performance significantly under poor conditions and makes the positioning system more useful for active safety systems. © 2018 IEEE

  • 429.
    Vedder, Benjamin
    et al.
    Department of Electronics, SP Technical Research Institute of Sweden, Borås, Sweden.
    Vinter, Jonny
    Department of Electronics, SP Technical Research Institute of Sweden, Borås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Using Simulation, Fault Injection and Property-Based Testing to Evaluate Collision Avoidance of a Quadcopter System2015In: 2015 IEEE International Conference on Dependable Systems and Networks Workshops (DSN-W) / [ed] Juan E. Guerrero, Los Alamitos, CA: IEEE Computer Society, 2015, p. 104-111Conference paper (Refereed)
    Abstract [en]

    In this work we use our testing platform based on FaultCheck and QuickCheck that we apply on a quadcopter simulator. We have used a hardware platform as the basis for the simulator and for deriving realistic fault models for our simulations. The quadcopters have a collision-avoidance mechanism that shall take over control when the situation becomes hazardous, steer away from the potential danger and then give control back to the pilot, thereby preventing collisions regardless of what the pilot does. We use our testing platform to randomly generate thousands of simulations with different input stimuli (using QuickCheck) for hundreds of quadcopters, while injecting faults simultaneously (using FaultCheck). This way, we can effectively adjust system parameters and enhance the collision-avoidance mechanism. © 2015 IEEE

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  • 430.
    Vinel, Alexey
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Belyaev, Evgeny
    Tampere University of Technology, Finland.
    Bellalta, Boris
    Universitat Pompeu Fabra, Spain.
    Hu, Honglin
    Shanghai Research Center for Wireless Communications, China.
    Live Video Streaming in Vehicular Networks2014In: Communication Technologies for Vehicles, Nets4Cars/Nets4Trains/Nets4Aircraft 2014 / [ed] A. Sikora, M. Berbineau, A. Vinel, M. Jonsson, A. Pirovano, M. Aguado, Heidelberg, Germany: Springer Berlin/Heidelberg, 2014, p. 156-162Conference paper (Refereed)
    Abstract [en]

    The coming years will see the adoption of IEEE 802.11p equipment, which enables broadband vehicle-to-vehicle and vehicle-to-roadside connectivity. The design and validation of prospective safety and infotainment applications in VANETs (Vehicular Ad-hoc NETworks) are currently areas of dynamic research. In this paper we introduce novel vehicular applications that are based on video transmission and targeted at improving road safety, efficiency and public security. We argue the case for the practical feasibility of the proposed applications in terms of the number of vehicles that can be supported with acceptable visual quality in VANETs environment. © 2014 Springer International Publishing.

  • 431.
    Vinel, Alexey
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Tampere University of Technology, Tampere, Finland.
    Belyaev, Evgeny
    Tampere University of Technology, Tampere, Finland.
    Lamotte, Olivier
    Hochschule für Technik Rapperswil, Rapperswil, Switzerland.
    Gabbouj, Moncef
    Tampere University of Technology, Tampere, Finland.
    Koucheryavy, Yevgeni
    Tampere University of Technology, Tampere, Finland.
    Egiazarian, Karen
    Tampere University of Technology, Tampere, Finland.
    Video transmission over IEEE 802.11p: Real-world measurements2013In: 2013 IEEE International Conference on Communications Workshops (ICC), Piscataway, NJ: IEEE Press, 2013, p. 505-509, article id 6649286Conference paper (Refereed)
    Abstract [en]

    IEEE 802.11p/ITG-G5 vehicle-to-vehicle communication technology, which enables the new class of safety and infotainment applications, is currently an emerging research topic in both industry and academia. The proposed spectrum allocation of 10 Mhz channels for DSRC (Dedicated Short Range Communication) in 5.9 GHz band for the USA and Europe allows considering the transmission of video information between vehicles as one of the grounding blocks for future automotive applications. Although several published works addressed the problems of video content delivery in VANETs (Vehicular Ad-hoc NETworks), no work has been reported on real-world measurements of visual quality for video being transmitted over the IEEE 802.11p vehicle-to-vehicle communication channel. This paper presents a real-time scalable video codec as well as the first results of visual quality measurements for the video information transmitted using the off-the-shelf Componentality FlexRoad DSRC equipment. © 2013 IEEE.

  • 432.
    Vinel, Alexey
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Chen, Wen-Shyen Eric
    ProphetStor Data Services, Milpitas, CA, USA.
    Xiong, Neal N.
    Department of Business and Computer Science, Southwestern Oklahoma State University, Weatherford, Oklahoma, USA.
    Rho, Seungmin
    Department of Media Software at Sungkyul University, Anyang, South Korea.
    Chilamkurti, Naveen
    Department of Computer Science and Telecommunications, La Trobe University, Melbourne, Australia.
    Vasilakos, Athanasios V.
    Luleå University of Technology, Luleå, Sweden.
    Enabling wireless communication and networking technologies for the internet of things2016In: IEEE wireless communications, ISSN 1536-1284, E-ISSN 1558-0687, Vol. 23, no 5, p. 8-9, article id 7721735Article in journal (Refereed)
  • 433.
    Vinel, Alexey
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Lan, Lin
    Hitachi Europe SAS, Sophia-Antipolis, France.
    Lyamin, Nikita
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Vehicle-to-vehicle communication in C-ACC/platooning scenarios2015In: IEEE Communications Magazine, ISSN 0163-6804, E-ISSN 1558-1896, Vol. 53, no 8, p. 192-197, article id 7180527Article in journal (Refereed)
    Abstract [en]

    Cooperative adaptive cruise control (C-ACC) and platooning are two emerging automotive intelligent transportation systems (ITS) applications. In this tutorial article we explain their principles, describe related ongoing standardization activities, and conduct performance evaluation of the underlying communication technology. © Copyright 2015 IEEE

  • 434.
    Vinel, Alexey
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Lyamin, Nikita
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Isachenkov, Pavel
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Modeling of V2V Communications for C-ITS Safety Applications: A CPS Perspective2018In: IEEE Communications Letters, ISSN 1089-7798, E-ISSN 1558-2558, Vol. 22, no 8, p. 1600-1603Article in journal (Refereed)
    Abstract [en]

    Tight coupling between the performance of vehicleto-vehicle (V2V) communications and the performance of Cooperative Intelligent Transportation Systems (C-ITS) safety applications is addressed. A Cyber-Physical System (CPS) analytical framework is developed that links the characteristics of V2V communications (such as packet loss probability and packet transmission delay) with the physical mobility characteristics of the vehicular system (such as safe inter-vehicular distance). The study is applied to the Day 1 C-ITS application, Emergency Electronic Brake Lights (EEBL), enabled by ETSI ITS-G5 and IEEE 802.11p standards. © 2018 IEEE

  • 435.
    Vinel, Alexey
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ma, Xiaomin
    Oral Roberts University, Tulsa, OK, USA.
    Huang, Dijiang
    Arizona State University, Tempe, AZ, USA.
    Guest Editors’ Introduction: Special Issue on Reliable and Secure VANETs2016In: IEEE Transactions on Dependable and Secure Computing, ISSN 1545-5971, E-ISSN 1941-0018, Vol. 13, no 1, p. 2-4Article in journal (Refereed)
  • 436.
    Vinel, Alexey
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Pettersson, Henrik
    Scania, Södertälje, Sweden.
    Lin, Lan
    Hitachi, Sophia Antipolis, France.
    Altintas, Onur
    Toyota, Tokyo, Japan.
    Gusikhin, Oleg
    Ford Research & Adv. Engineering, Dearborn, MI, United States.
    Vehicular networking for autonomous driving: [Guest Editorial]2015In: IEEE Communications Magazine, ISSN 0163-6804, E-ISSN 1558-1896, Vol. 53, no 12, p. 62-63Article in journal (Refereed)
  • 437.
    Wang, Kun
    et al.
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    Du, Miao
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    Sun, Yanfei
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Zhang, Yan
    University of Oslo, Oslo, Norway & Simula Research Laboratory, Fornebu, Norway.
    Attack Detection and Distributed Forensics in Machine-to-Machine Networks2016In: IEEE Network, ISSN 0890-8044, E-ISSN 1558-156X, Vol. 30, no 6, p. 49-55Article in journal (Refereed)
    Abstract [en]

    The advanced idea of machine-to-machine technology has attracted a new period of network revolution, evolving into a method to monitor and control global industrial user assets, machines, and the production process. M2M networks are considered to be the intelligent connection and communication between machines. However, the security issues have been further amplified with the development of M2M networks. Consequently, it is essential to pour attention into attack detection and forensics problems in M2M networks. This article puts forward the hybrid attack detection and forensics model in M2M networks. It contains two modules: the attack detection module and the forensics analysis module. In addition, we present a distributed anti-honeypot-based forensics strategy to cope with DDoS attacks in the forensics analysis module. Finally, we also discuss some challenges in M2M network security and forensics.

  • 438.
    Wang, Kun
    et al.
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    Gu, Liqiu
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    He, Xiaoming
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    Guo, Song
    Hong Kong Polytechnic University, Hong Kong, Hong Kong.
    Sun, Yanfei
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Shen, Jian
    Nanjing University of Information Science and Technology, Nanjing, China.
    Distributed Energy Management for Vehicle-to-Grid Networks2017In: IEEE Network, ISSN 0890-8044, E-ISSN 1558-156X, Vol. 31, no 2, p. 22-28Article in journal (Refereed)
    Abstract [en]

    Making full use of V2G services, EVs with batteries may assist the smart grid in alleviating peaks of energy consumption. Aiming to develop a systematic understanding of the interplay between smart grid and EVs, an architecture for the V2G networks with the EV aggregator is designed to maintain the balance between energy suppliers (the grid side) and consumers (the EV side). We propose a combined control and communication approach considering distributed features and vehicle preferences in order to ensure efficient energy transfer. In our model, the integrated communication and control unit can achieve realtime and intelligent management with the logic controller and collected data. On the consumers' side, we theoretically analyze how to satisfy the charging constraints that we incorporate in the form of willingness to pay, and propose a distributed framework to coordinate the energy delivery behaviors for satisfying service demands. Moreover, illustrative results indicate that the proposed approach can yield higher revenue than the conventional pricing mechanism in V2G networks.

  • 439.
    Wang, Kun
    et al.
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    Wang, Yunqi
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    Hu, Xiaoxuan
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    Sun, Yanfei
    Nanjing University of Posts and Telecommunications, Nanjing, China.
    Deng, Der-Jiunn
    National Changhua University of Education, Changhua City, Taiwan.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Zhang, Yan
    University of Oslo, Oslo, Norway & Simula Research Laboratory, Fornebu, Norway.
    Wireless Big Data Computing in Smart Grid2017In: IEEE wireless communications, ISSN 1536-1284, E-ISSN 1558-0687, Vol. 24, no 2, p. 58-64Article in journal (Refereed)
    Abstract [en]

    The development of smart grid brings great improvement in the efficiency, reliability, and economics to power grid. However, at the same time, the volume and complexity of data in the grid explode. To address this challenge, big data technology is a strong candidate for the analysis and processing of smart grid data. In this article, we propose a big data computing architecture for smart grid analytics, which involves data resources, transmission, storage, and analysis. In order to enable big data computing in smart grid, a communication architecture is then described consisting of four main domains. Key technologies to enable big-data-aware wireless communication for smart grid are investigated. As a case study of the proposed architecture, we introduce a big-data- enabled storage planning scheme based on wireless big data computing. A hybrid approach is adopted for the optimization including GA for storage planning and a game theoretic inner optimization for daily energy scheduling. Simulation results indicate that the proposed storage planning scheme greatly reduce.

  • 440.
    Wang, Rui
    et al.
    Halmstad University, School of Information Technology.
    Zhang, Hequn
    Halmstad University, School of Information Technology.
    Larsson, Tony
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Region-based Geocast Routing Protocols for VANETs: Summary, Evaluation Methods and Simulation Models2014In: 2014 International Conference on Connected Vehicles and Expo (ICCVE), Piscataway, NJ: IEEE Press, 2014, p. 731-738, article id 7297646Conference paper (Refereed)
    Abstract [en]

    Vehicular Ad hoc Networks (VANETs) is a technology to support communication among vehicles or between vehicles and infrastructure in order to exchange traffic information and avoid accidents. Many applications in VANETs need to transmit messages to vehicles within a specific geographic region. This behaviour is called Geocast. Several Geocast routing protocols have been proposed for VANETs. In this paper, some important and representative Geocast routing protocols are summarized and theoretically compared. In order to evaluate the performance of these protocols, the evaluation methods are also defined, which include both the Packet Delivery Ratio (PDR) and the Packet Delivery Time (PDT). Additionally, some important and new models, such as the influences of city lights, and the distance between buildings potentially acting as free line of sight obstacles, are proposed to create a more realistic city environment for Geocast routing simulation. © 2014 IEEE

  • 441.
    Wang, Yan
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Domain-Specific Language for Protocol Stack Implementation in Embedded Systems2011Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Embedded network software has become increasingly interesting for both research and business as more and more networked embedded systems emerge. Well-known infrastructure protocol stacks are reimplemented on new embedded hardware and software architectures. New requirements of modern applications and devices require to implement newly designed or revised protocols. However, implementing protocol stacks for embedded systems remains a time-consuming and error-prone task due to the complexity and performancecritical nature of network software. It is even more so when targeting resource constrained embedded systems: implementations have to minimize energy consumption, memory usage etc., while programming efficiency is needed to improve on time-to-market, scalability, maintainability and product evolution. Therefore, it is worth researching on how to make protocol stack implementations for embedded systems both easier and more likely to be correct within the resource limits.

    In the work presented in this thesis, we take a language-based approach and aim to facilitate the implementation of protocol stacks while realizing performance demands and being aware of energy consumption and memory usage within the constraints imposed by embedded systems. We give background on DSL implementation techniques, investigate common practices in network protocol development to determine the potential of domain-specifi languages (DSLs) for embedded network software, and propose a domain-specifi embedded language (DSEL), Protege (Protocol Implementation Generator), for declaratively describing overlaid protocol stacks. In Protege, a high-level packet specification is dually compiled into an internal data representation for protocol logic implementation, and packet processing methods which are then integrated into the dataflow framework of a protocol overlay specification. Constructs for finite state machines allow to specify protocol logic in a concise manner, close to the protocol specification style. Protege specifications are compiled to highly portable C code for various architectures.

    Four attached scientific papers report our main results in more detail: an embedded implementation of the data description calculus in Haskell, a compilation framework for generating packet processing code with overlays, the domain-specific language Protege in overview (including embedding techniques and runtime system features), and a real-world case study implementing an industrial application protocol.

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  • 442.
    Wang, Yan
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Gaspes, Veronica
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Compositional Implementation of Modbus in Protege2011In: 6th IEEE International Symposium on Industrial Embedded Systems (SIES), 2011, Piscataway, N.J.: IEEE Press, 2011, p. 123-131Conference paper (Refereed)
    Abstract [en]

    Network protocols today play a major role in embedded software for industrial automation, with constant efforts to adapt existing device software to new emerging standards. In earlier work, we have proposed a compilation-based approach using a domain-specific language, Protege, which automatically generates protocol stack implementations in C from modular high-level descriptions. In this paper, we provide a case study of the Protege language in an industrial setting. We have implemented the Modbus protocol over TCP/IP and over serial line, and tested it using an industrial gateway. Our implementation demonstrates Protege's advantages for software productivity, easy maintenance and code reuse, and it achieves many desirable properties of industrial embedded network software.

  • 443.
    Wang, Yan
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Gaspes, Veronica
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Domain-Specific Language Approach to Protocol Stack Implementation2010Conference paper (Refereed)
    Abstract [en]

    This paper describes a domain-specific language embeddedin Haskell, IPS, for the implementation of protocol stacks for embeddedsystems. IPS profits from Haskell’s features and generates C implementationsby embedded compilation.

  • 444.
    Wang, Yan
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Gaspes, Veronica
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    An embedded language for programming protocol stacks in embedded systems2011In: PEPM '11: proceedings of the 20th ACM SIGPLAN Workshop on Partial Evaluation and Semantics-Based Program Manipulation, January 24, 2011, Austin, Texas, USA, New York, NY, USA: ACM Press, 2011, p. 63-72Conference paper (Refereed)
    Abstract [en]

    Protocol stack specifications are well-structured documents that follow a number of conventions and notations that have proven very useful for the design and dissemination of communication protocols. Protocol stack implementations on the other hand, are done in low-level languages, using error-prone programming techniques resulting in programs that are difficult to relate to the specifications, difficult to maintain, modify, extend and reuse. To overcome these problems we propose a domain-specific language that provides abstractions close to the notations used in protocol specifications. From descriptions in our language we generate C programs that can be integrated with other systems software. The language provides constructs to describe packet formats, including physical layout, constraints and dependencies. It also provides constructs for state machines and for layering protocols into stacks. Experiments show that the C programs we generate are comparable in performance and binary size to hand-crafted C programs.

  • 445.
    Wang, Yan
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Gaspes, Veronica
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Integrating a data description language with protocol stack development2009In: Proceedings of the IASTED International Conference on Modelling, Simulation, and Identification, MSI 2009 / [ed] H. Ma and S. Narayanan, Anaheim, Calif.: ACTA Press, 2009, p. 8-Conference paper (Refereed)
    Abstract [en]

    Communication software, most notoriously protocolstacks, are an area of growing interest. Many companiesimplement new or revised protocols for new applicationrequirements, and reimplement well-known infrastructureprotocol stacks to accomodate to new hardware andsoftware platforms. However, due to the complexity andperformance-critical nature of communication software,implementing protocol stacks remains a time-consumingand error-prone task with considerable impact on time tomarket, scalability and maintainance. The work at handinvestigates how to provide program development supportfor protocol stack implementation to make it easier andmore likely to be correct while respecting non-functionalconstraints. We present a language-based approach for theimplementation of protocol stacks. We define a domainspecificembedded language, IPS, for declaratively describingoverlaid protocol stacks. In IPS a high-level packetspecification is described using a data description languagewhich is compiled into a.) an internal data representation,and b.) packet processing functions in C. Both are then integratedinto the dataflow framework of a protocol overlayspecification. IPS generates highly portable C code for variousarchitectures from this source. We present the compilationframework for generating packet processing andprotocol logic code, and a preliminary evaluation.

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  • 446.
    Wecksten, Mattias
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Vasell, Jonas
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Jonsson, Magnus
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Towards a tool for derivation of implementation constraints2004In: Ninth IEEE International Conference on Engineering Complex Computer Systems, 2004. Proceedings, Piscataway, N.J.: IEEE , 2004, p. 119-127Conference paper (Refereed)
    Abstract [en]

    An increasing concern in the development of embedded systems is that fundamental design problems often remain undetected until the final tests, after implementation and integration of all components, or maybe even later - at runtime. This is particularly important when it comes to meeting nonfunctional constraints such as performance or resource utilization requirements. Correcting problems with their sources in design, after implementation, may be very costly as it often requires both redesign and re-implementation. Therefore, much effort has been put into the development of methods and tools that help system designers and developers to detect problems as early as possible during system development. This paper contributes with an addition to that field by presenting and evaluating the practical usefulness of a method that makes it possible to detect problems in system design and dimensioning, even before all components of the system have been fully implemented. Evaluation of the proposed method has been done through 17 different case studies with different characteristics, focusing particularly on realtime latency requirements for tasks on homogeneous single bus platforms. The evaluation indicates a practical method that can be turned into a powerful tool. The presented principles can be extended to wider classes of constraints and systems.

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  • 447.
    Weckstén, Mattias
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Jonsson, Magnus
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Vasell, J.
    Generic Systems Sweden AB.
    Derivation of implementation constraints - implementation simulation and treatment of multiple design choices2005In: Proceedings: 10th IEEE International Conference on Engineering of Complex Computer Systems, ICECCS 2005, 16-20 June 2005, Shanghai, China, Los Alamitos, Calif.: IEEE Computer Society, 2005, p. 459-466Conference paper (Refereed)
    Abstract [en]

    The industrial use of ad hoc implementation methods for non-functional constrained tasks has resulted in unnecessary expensive projects. In some cases, ad hoc methods result in overly many iterations to be made and in some severe cases, total project breakdown. To be able to solve these problems a method has been developed to derive end-to-end non-functional constraints, such as timing requirements, to task-level constraints and to promote this information to the implementation phase of the project. For a tool, as the one described above, to be really useful it is important to be able to show that there is a potential cost reduction to be made. To be able to show that a certain implementation method costs less in work hours than to use an ad hoc implementation method, a model for implementation simulation with support for multiple implementation alternatives has been developed. The experiments show that using the budget based implementation method leads to a significant cost reduction in most cases, compared to the ad hoc method. As far as we know, no similar experiments have been done to compare implementation methods.

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  • 448.
    Wehrmeister, Marco A.
    et al.
    Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil.
    Pignaton de Freitas, Edison
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Pereira, Carlos E.
    Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil.
    An Infrastructure for UML-Based Code Generation Tools2009In: Analysis, architectures and modelling of embedded systems: Third IFIP TC 10 International Embedded Systems Symposium, IESS 2009, Langenargen, Germany, September 14-16, 2009, proceedings / [ed] Rettberg, A Zanella, MC Rammig, FJ, New York: Springer-Verlag New York, 2009, p. 32-43Conference paper (Refereed)
    Abstract [en]

    The use of Model-Driven Engineering (MDE) techniques in the domain of distributed embedded real-time systems are gain importance in order to cope with the increasing design complexity of such systems. This paper discusses an infrastructure created to build GenERTiCA, a flexible tool that supports a MDE approach, which uses aspect-oriented concepts to handle nonfunctional requirements from embedded and real-time systems domain. GenERTiCA generates source code from UML models, and also performs weaving of aspects, which have been specified within the UML model. Additionally, this paper discusses the Distributed Embedded Real-Time Compact Specification (DERCS), a PIM created to support UML-based code generation tools. Some heuristics to transform UML models into DERCS, which have been implemented in GenERTiCA, are also discussed.

  • 449.
    Wehrmeister, Marco A.
    et al.
    Instituto de Informática, Federal University of Rio Grande do Sul, Porto Alegre, Brazil.
    Pignaton de Freitas, Edison
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Instituto de Informática, Federal University of Rio Grande do Sul, Porto Alegre, Brazil.
    Pereira, Carlos E.
    Dep. Engenharia Elétrica, Federal University of Rio Grande do Sul, Porto Alegre, Brazil.
    Using GenERTiCA to generation code from RT-UML: A case study2009In: Elsevier IFAC Publications / IFAC Proceedings series, ISSN 1474-6670, Vol. 13, no PART 1, p. 674-679Article in journal (Refereed)
    Abstract [en]

    Tool support is essential to allow the use of Model-Driven Engineering (MDE) in the design of distributed embedded real-time systems. GenERTiCA is a flexible tool that supports a MDE approach, which uses concepts of Aspect-Oriented Development (AOD) to handle non-functional requirements from real-time and embedded systems domain. This paper presents a comprehensive case study that illustrates GenERTiCA usage to generate source code from UML models. GenERTiCA also performs aspects weaving using aspect’s information specified in UML models. Results regarding source code generation for a Java platform based on the Real-Time Specification for Java (RTSJ) are presented. Additionally, this paper discusses the implementation of some aspects of a high-level aspects framework, named DERAF, using the mentioned platform. © 2009 IFAC.

  • 450.
    Wolkerstorfer, M.
    et al.
    FTW, Österrike.
    Nordström, Tomas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Coverage Optimization in DSL Networks by Low-Complexity Discrete Spectrum Balancing2011Conference paper (Refereed)
    Abstract [en]

    Spectrum balancing is an established optimization approach in multi-carrier digital subscriber line (DSL) systems. It has previously been applied to very different performance objectives such as sum-rate, min-rate, or fairness maximization and sum-power minimization. In this work we study the maximization of the service coverage, which will be defined as the number of DSL lines which can be granted an operator-specified high-bandwidth service. The proposed algorithm is based on a previously described mathematical decomposition framework. We extend this framework for our new problem and enhance its scalability by various low-complexity heuristics. Simulations demonstrate the applicability of our algorithm for DSL networks of realistic sizes. More precisely, our results obtained in thousand 25 user near-far DSL scenarios show an average gain in service coverage of more than 13% compared to state-of-the-art sum-rate maximizing spectrum balancing algorithms. © 2011 IEEE.

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