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  • 351.
    Ramazanali, Hawar
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Saab Training and Simulation, Huskvarna, Sweden.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Tuning of LTE/LTE-A DRX parameters2016In: 2016 IEEE 21st International Workshop on Computer Aided Modelling and Design of Communication Links and Networks (CAMAD), Piscataway, NJ: IEEE, 2016, p. 95-100Conference paper (Refereed)
    Abstract [en]

    The tradeoff between the power saving and the queuing delay in LTE/LTE-A radio devices with Discontinuous Reception (DRX) Mechanism is discussed. Two optimization problems to tune the DRX parameters are formulated. An optimal performance determined by exhaustive search over a large parameter set and a reduced parameter set, obtained by disabling short DRX cycles, is compared.

  • 352.
    Ramazanali, Hawar
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). SAAB Training and Simulation, Huskvarna, Sweden.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Yavuz, Emre
    Ericsson AB, Stockholm, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Modeling of LTE DRX in RRC Idle state2017In: 2017 IEEE 22nd International Workshop on Computer Aided Modeling and Design of Communication Links and Networks (CAMAD), 2017Conference paper (Refereed)
    Abstract [en]

    In LTE/LTE-A the Discontinuous Reception (DRX) mechanism is the main approach for power saving in User Equipments (UEs) when in Connected and Idle mode. In this paper, an Idle mode DRX mechanism model is proposed also enabling evaluation of closely related mechanisms such as paging and Tracking Area Update (TAU). Two performance metrics are derived, namely the reachability delay and the power saving factor. © Copyright 2017 IEEE

  • 353.
    Rezk, Nesma
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Exploring Efficient Implementations of Deep Learning Applications on Embedded Platforms2020Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    The promising results of deep learning (deep neural network) models in many applications such as speech recognition and computer vision have aroused a need for their realization on embedded platforms. Augmenting DL (Deep Learning) in embedded platforms grants them the support to intelligent tasks in smart homes, mobile phones, and healthcare applications. Deep learning models rely on intensive operations between high precision values. In contrast, embedded platforms have restricted compute and energy budgets. Thus, it is challenging to realize deep learning models on embedded platforms.

    In this thesis, we define the objectives of implementing deep learning models on embedded platforms. The main objective is to achieve efficient implementations. The implementation should achieve high throughput, preserve low power consumption, and meet real-time requirements.The secondary objective is flexibility. It is not enough to propose an efficient hardware solution for one model. The proposed solution should be flexible to support changes in the model and the application constraints. Thus, the overarching goal of the thesis is to explore flexible methods for efficient realization of deep learning models on embedded platforms.

    Optimizations are applied to both the DL model and the embedded platform to increase implementation efficiency. To understand the impact of different optimizations, we chose recurrent neural networks (as a class of DL models) and compared its' implementations on embedded platforms. The comparison analyzes the optimizations applied and the corresponding performance to provide conclusions on the most fruitful and essential optimizations. We concluded that it is essential to apply an algorithmic optimization to the model to decrease it's compute and memory requirement, and it is essential to apply a memory-specific optimization to hide the overhead of memory access to achieve high efficiency. Furthermore, it has been revealed that many of the work understudy focus on implementation efficiency, and flexibility is less attempted.

    We have explored the design space of Convolutional neural networks (CNNs) on Epiphany manycore architecture. We adopted a pipeline implementation of CNN that relies on the on-chip memory solely to store the weights. Also, the proposed mapping supported both ALexNet and GoogleNet CNN models, varying precision for weights, and two memory sizes for Epiphany cores. We were able to achieve competitive performance with respect to emerging manycores.

    As a part of the work in progress, we have studied a DL-architecture co-design approach to increase the flexibility of hardware solutions. A flexible platform should support variations in the model and variations in optimizations. The optimization method should be automated to respond to the changes in the model and application constraints with minor effort. Besides, the mapping of the models on embedded platforms should be automated as well.

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  • 354.
    Rezk, Nesma
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    ModelFlex: Parameter Tuning for Flexible Design of Deep Learning AcceleratorsManuscript (preprint) (Other academic)
    Abstract [en]

    Algorithmic optimizations are applied to neural networks models to decrease their compute and memory requirements for efficient realization on embedded platforms. A feedback form the target platform during the optimization process can increase the benefit of these optimizations. In this paper, we propose a method for hardware guided optimizations to recurrent neural networks. The method is automated to respond to changes in the model or the application constraints with minimal effort. Also, a hybrid of three optimizations is applied to the base RNN model to increase the search space for a feasible solution and increase the chance of skipping retraining.

  • 355.
    Rezk, Nesma
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Purnaprajna, Madhura
    Amrita Vishwa Vidyapeetham, Bengaluru, India.
    Nordström, Tomas
    Department of Applied Physics and Electronics (TFE), Umeå University, Umeå, Sweden.
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Recurrent Neural Networks: An Embedded Computing Perspective2020In: IEEE Access, E-ISSN 2169-3536, Vol. 8, p. 57967-57996Article in journal (Refereed)
    Abstract [en]

    Recurrent Neural Networks (RNNs) are a class of machine learning algorithms used for applications with time-series and sequential data. Recently, there has been a strong interest in executing RNNs on embedded devices. However, difficulties have arisen because RNN requires high computational capability and a large memory space. In this paper, we review existing implementations of RNN models on embedded platforms and discuss the methods adopted to overcome the limitations of embedded systems. We will define the objectives of mapping RNN algorithms on embedded platforms and the challenges facing their realization. Then, we explain the components of RNN models from an implementation perspective. We also discuss the optimizations applied to RNNs to run efficiently on embedded platforms. Finally, we compare the defined objectives with the implementations and highlight some open research questions and aspects currently not addressed for embedded RNNs. Overall, applying algorithmic optimizations to RNN models and decreasing the memory access overhead is vital to obtain high efficiency. To further increase the implementation efficiency, we point up the more promising optimizations that could be applied in future research. Additionally, this article observes that high performance has been targeted by many implementations, while flexibility has, as yet, been attempted less often. Thus, the article provides some guidelines for RNN hardware designers to support flexibility in a better manner. © 2020 IEEE.

  • 356.
    Rezk, Nesma
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Purnaprajna, Madhura
    Amrita University, Bengaluru, India.
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    E€iffcient Implementation of Convolution Neural Networks Inference On Manycore Architectures2017Conference paper (Refereed)
    Abstract [en]

    The convolution module of convolution neural networks is highly computation demanding. In order to execute a neural network inference on embedded platforms, an ecient implementation of the convolution is required. Low precision parameters can provide an implementation that requires less memory, less computation time, and less power consumption. Nevertheless, streaming the convolution computation over parallelized processing units saves a lot of memory, which is a key concern in memory constrained embedded platforms. In this paper, we show how the convolution module can be implemented on Epiphany manycore architecture. Low precision parameters are used with ternary weights of +1, 0, and -1 values. The computation is done through a pipeline by streaming data through processing units. The proposed approach decreases the memory requirements for CNN implementation and could reach up to 282 GOPS and up to 5.6 GOPs/watt.

  • 357.
    Rezk, Nesma
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Purnaprajna, Madhura
    Amrita University, Bengaluru, India.
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Streaming Tiles: Flexible Implementation of Convolution Neural Networks Inference on Manycore Architectures2018In: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Los Alamitos: IEEE Computer Society, 2018, p. 867-876Conference paper (Refereed)
    Abstract [en]

    Convolution neural networks (CNN) are extensively used for deep learning applications such as image recognition and computer vision. The convolution module of these networks is highly compute-intensive. Having an efficient implementation of the convolution module enables realizing the inference part of the neural network on embedded platforms. Low precision parameters require less memory, less computation time, and less power consumption while achieving high classification accuracy. Furthermore, streaming the data over parallelized processing units saves a considerable amount of memory, which is a key concern in memory constrained embedded platforms. In this paper, we explore the design space for streamed CNN on Epiphany manycore architecture using varying precisions for weights (ranging from binary to 32-bit). Both AlexNet and GoogleNet are explored for two different memory sizes of Epiphany cores. We are able to achieve competitive performance for both Alexnet and GoogleNet with respect to emerging manycores. Furthermore, the effects of different design choices in terms of precision, memory size, and the number of cores are evaluated by applying the proposed method.

  • 358.
    Ruzicka, Theophil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Model based Design of a Sailboat Autopilot2017Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
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  • 359.
    Sajadian, S.
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Ibrahim, A.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    de Freitas, Edison Pignaton
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Larsson, Tony
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Improving Connectivity of Nodes in Mobile WSN2011In: Advanced Information Networking and Applications (AINA), 2011 IEEE International Conference on, Los Alamitos: IEEE Computer Society, 2011, p. 364-371Conference paper (Refereed)
    Abstract [en]

    How to measure and maintain connectivity is an important issue in ad hoc networks. A special case of such network is Wireless Sensor Networks (WSN), which are often deployed in harsh environments and also susceptible to a number of problems that may negatively affect the connectivity among the nodes. An additional factor that increases the cost of connectivity maintenance in ad hoc networks is when the nodes can move. When it comes to the WSN domain, this aspect is still more problematic, as the often small sensor nodes have in general a limited energy budget, and then should not use too much energy in the management of their connectivity. The goal of this work is to choose a topology for mobile WSN and improve the network connectivity as a whole while considering and influencing the energy consumption among all the nodes in the network. Different network topologies are considered and discussed. After evaluation of the pros and cons of the estimation quality when applied to each studied topology, a clustered hierarchical algorithm was chosen for network deployment. By means of a link estimator and considering different variables, a metric have been defined to estimate the link reliability. As a result, improved network connectivity is reported.

  • 360.
    Salama, Cherif
    et al.
    Ain Shams University, Cairo, Egypt.
    Taha, Walid
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Rice University, Houston, Texas, USA.
    Increasing Verilog’s Generative Power2014Conference paper (Refereed)
    Abstract [en]

    To cope with more complex circuits, well-understood higher-level abstraction mechanisms are needed. Verilog is already equipped with promising generative constructs making it possible to concisely describe a family of circuits as a parameterized module; however these constructs suffer from limited expressivity even in the latest IEEE standard. In this paper, we address generative constructs expressivity limitations, identifying the key extensions needed to overcome these limitations, and showing how to incorporate them in Verilog in a disciplined, backward-compatible way.

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  • 361.
    Sardis, Fragkiskos
    et al.
    Department of Informatics, King’s College London, London, United Kingdom.
    Mapp, Glenford
    School of Science and Technology, Middlesex University, London, United Kingdom.
    Loo, Jonathan
    School of Science and Technology, Middlesex University, London, United Kingdom.
    Aiash, Mahdi
    School of Science and Technology, Middlesex University, London, United Kingdom.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Investigating a Mobility-Aware QoS Model for Multimedia Streaming Rate Adaptation2015In: Journal of Electrical and Computer Engineering, ISSN 2090-0147, E-ISSN 2090-0155, Vol. 2015, article id 548638Article in journal (Refereed)
    Abstract [en]

    Supporting high quality multimedia streaming on wireless devices poses several challenges compared to wired networks due to the high variance in network performance encountered in the mobile environment. Although rate adaptation is commonly used in multimedia applications to compensate for fluctuations in network performance, it is a reactive mechanism which is not aware of the frequently changing connectivity that may occur on mobile devices. This paper proposed a performance evaluation model for multimedia streaming applications that is aware of user mobility and network performance. We presented an example of mathematical solution to the model and demonstrated the functionality using common mobility and connectivity examples that may be found in an urban environment. The proposed model is evaluated based on this functionality and how it may be used to enhance application performance. © 2015 Fragkiskos Sardis et al.

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  • 362.
    Sardis, Fragkiskos
    et al.
    School of Science and Technology, Middlesex University, London, United Kingdom.
    Mapp, Glenford
    School of Science and Technology, Middlesex University, London, United Kingdom.
    Loo, Jonathan
    School of Science and Technology, Middlesex University, London, United Kingdom.
    Aiash, Mahdi
    School of Science and Technology, Middlesex University, London, United Kingdom.
    Vinel, Alexey
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    On the Investigation of Cloud-Based Mobile Media Environments With Service-Populating and QoS-Aware Mechanisms2013In: IEEE transactions on multimedia, ISSN 1520-9210, E-ISSN 1941-0077, Vol. 15, no 4, p. 769-777Article in journal (Refereed)
    Abstract [en]

    Recent advances in mobile devices and network technologies have set new trends in the way we use computers and access networks. Cloud Computing, where processing and storage resources are residing on the network is one of these trends. The other is Mobile Computing, where mobile devices such as smartphones and tablets are believed to replace personal computers by combining network connectivity, mobility, and software functionality. In the future, these devices are expected to seamlessly switch between different network providers using vertical handover mechanisms in order to maintain network connectivity at all times. This will enable mobile devices to access Cloud Services without interruption as users move around. Using current service delivery models, mobile devices moving from one geographical location to another will keep accessing those services from the local Cloud of their previous network, which might lead to moving a large volume of data over the Internet backbone over long distances. This scenario highlights the fact that user mobility will result in more congestion on the Internet. This will degrade the Quality of Service and by extension, the Quality of Experience offered by the services in the Cloud and especially multimedia services that have very tight temporal constraints in terms of bandwidth and jitter. We believe that a different approach is required to manage resources more efficiently, while improving the Quality of Service and Quality of Experience of mobile media services. This paper introduces a novel concept of Cloud-Based Mobile Media Service Delivery in which services run on localized public Clouds and are capable of populating other public Clouds in different geographical locations depending on service demands and network status. Using an analytical framework, this paper argues that as the demand for specific services increases in a location, it might be more efficient to move those services closer to that location. This will prevent the Internet backbone from experiencing high traffic loads due to multimedia streams and will offer service providers an automated resource allocation and management mechanism for their services. © 1999-2012 IEEE.

  • 363.
    Savas, Süleyman
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Hardware/Software Co-Design of Heterogeneous Manycore Architectures2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    In the era of big data, advanced sensing, and artificial intelligence, the required computation power is provided mostly by multicore and manycore architectures. However, the performance demand keeps growing. Thus the computer architectures need to continue evolving and provide higher performance. The applications, which are executed on the manycore architectures, are divided into several tasks to be mapped on separate cores and executed in parallel. Usually these tasks are not identical and may be executed more efficiently on different types of cores within a heterogeneous architecture. Therefore, we believe that the heterogeneous manycores are the next step for the computer architectures. However, there is a lack of knowledge on what form of heterogeneity is the best match for a given application or application domain. This knowledge can be acquired through designing these architectures and testing different design configurations. However, designing these architectures is a great challenge. Therefore, there is a need for an automated design method to facilitate the architecture design and design space exploration to gather knowledge on architectures with different configurations. Additionally, it is already difficult to program manycore architectures efficiently and this difficulty will only increase further with the introduction of heterogeneity due to the increase in the complexity of the architectures, unless this complexity is somehow hidden. There is a need for software development tools to facilitate the software development for these architectures and enable portability of the same software across different manycore platforms.

    In this thesis, we first address the challenges of the software development for manycore architectures. We evaluate a dataflow language (CAL) and a source-to-source compilation framework (Cal2Many) with several case studies in order to reveal their impact on productivity and performance of the software. The language supports task level parallelism by adopting actor model and the framework takes CAL code and generates implementations in the native language of several different architectures.

    In order to address the challenge of custom hardware development, we first evaluate a commercial manycore architecture namely Epiphany and identify its demerits. Then we study manycore architectures in order to reveal possible uses of heterogeneity in manycores and facilitate choice of architecture for software and hardware development. We define a taxonomy for manycore architectures that is based on the levels of heterogeneity they contain and discuss the benefits and drawbacks of these levels. We finally develop and evaluate a design method to design heterogeneous manycore architectures customized based on application requirements. The architectures designed with this method consist of cores with application specific accelerators. The majority of the design method is automated with software tools, which support different design configurations in order to increase the productivity of the hardware developer and enable design space exploration.

    Our results show that the dataflow language, together with the software development tool, decreases software development efforts significantly (25-50%), while having a small impact (2-17%) on the performance. The evaluation of the design method reveal that the performance of automatically generated accelerators is between 96-100% of the performance of their manually developed counterparts. Additionally, it is possible to increase the performance of the architectures by increasing the number of cores and using application specific accelerators, usually with a cost on the area usage. However, under certain circumstances, using accelerator may lead to avoiding usage of large general purpose components such as the floating-point unit and therefore improves the area utilization. Eventually, the final impact on the performance and area usage depends on the configurations. When compared to the Epiphany architecture, which is a commercial homogeneous manycore, the generated manycores show competitive results. We can conclude that the automated design method simplifies heterogeneous manycore architecture design and facilitates design space exploration with the use of configurable parameters.

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    SavasPhDThesis
  • 364.
    Savas, Süleyman
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Utilizing Heterogeneity in Manycore Architectures for Streaming Applications2017Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    In the last decade, we have seen a transition from single-core to manycore in computer architectures due to performance requirements and limitations in power consumption and heat dissipation. The first manycores had homogeneous architectures consisting of a few identical cores. However, the applications, which are executed on these architectures, usually consist of several tasks requiring different hardware resources to be executed efficiently. Therefore, we believe that utilizing heterogeneity in manycores will increase the efficiency of the architectures in terms of performance and power consumption. However, development of heterogeneous architectures is more challenging and the transition from homogeneous to heterogeneous architectures will increase the difficulty of efficient software development due to the increased complexity of the architecture. In order to increase the efficiency of hardware and software development, new hardware design methods and software development tools are required. Additionally, there is a lack of knowledge on the performance of applications when executed on manycore architectures.

    The transition began with a shift from single-core architectures to homogeneous multicore architectures consisting of a few identical cores. It now continues with a shift from homogeneous architectures with identical cores to heterogeneous architectures with different types of cores specialized for different purposes. However, this transition has increased the complexity of architectures and hence the complexity of software development and execution. In order to decrease the complexity of software development, new software tools are required. Additionally, there is a lack of knowledge on what kind of heterogeneous manycore design is most efficient for different applications and what are the performances of these applications when executed on current commercial manycores.

    This thesis studies manycore architectures in order to reveal possible uses of heterogeneity in manycores and facilitate choice of architecture for software and hardware developers. It defines a taxonomy for manycore architectures that is based on the levels of heterogeneity they contain and discusses benefits and drawbacks of these levels. Additionally, it evaluates several applications, a dataflow language (CAL), a source-to-source compilation framework (Cal2Many), and a commercial manycore architecture (Epiphany). The compilation framework takes implementations written in the dataflow language as input and generates code targetting different manycore platforms. Based on these evaluations, the thesis identifies the bottlenecks of the architecture. It finally presents a methodology for developing heterogeneoeus manycore architectures which target specific application domains.

    Our studies show that using different types of cores in manycore architectures has the potential to increase the performance of streaming applications. If we add specialized hardware blocks to a core, the performance easily increases by 15x for the target application while the core size increases by 40-50% which can be optimized further. Other results prove that dataflow languages, together with software development tools, decrease software development efforts significantly (25-50%) while having a small impact (2-17%) on the performance.

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  • 365.
    Savas, Süleyman
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Gebrewahid, Essayas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nordström, Tomas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Yang, Mingkun
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    An Evaluation of Code Generation of Dataflow Languages on Manycore Architectures2014In: RTCSA 2014: 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, Piscataway, NJ: IEEE Press, 2014, article id 6910501Conference paper (Refereed)
    Abstract [en]

    Today computer architectures are shifting from single core to manycores due to several reasons such as performance demands, power and heat limitations. However, shifting to manycores results in additional complexities, especially with regard to efficient development of applications. Hence there is a need to raise the abstraction level of development techniques for the manycores while exposing the inherent parallelism in the applications. One promising class of programming languages is dataflow languages and in this paper we evaluate and optimize the code generation for one such language, CAL. We have also developed a communication library to support the inter-core communication.The code generation can target multiple architectures, but the results presented in this paper is focused on Adapteva's many core architecture Epiphany.We use the two-dimensional inverse discrete cosine transform (2D-IDCT) as our benchmark and compare our code generation from CAL with a hand-written implementation developed in C. Several optimizations in the code generation as well as in the communication library are described, and we have observed that the most critical optimization is reducing the number of external memory accesses. Combining all optimizations we have been able to reduce the difference in execution time between auto-generated and hand-written implementations from a factor of 4.3x down to a factor of only 1.3x. ©2014 IEEE.

  • 366.
    Savas, Süleyman
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Hertz, Erik
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nordström, Tomas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis2017In: 2017 IEEE Computer Society Annual Symposium on VLSI: ISVLSI 2017 / [ed] Michael Hübner, Ricardo Reis, Mircea Stan & Nikolaos Voros, Los Alamitos: IEEE, 2017Conference paper (Refereed)
    Abstract [en]

    This paper proposes a novel method for performing division on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is based on an inverter, implemented as a combination of Parabolic Synthesis and second-degree interpolation, followed by a multiplier. It is implemented with and without pipeline stages individually and synthesized while targeting a Xilinx Ultrascale FPGA.

    The implementations show better resource usage and latency results when compared to other implementations based on different methods. In case of throughput, the proposed method outperforms most of the other works, however, some Altera FPGAs achieve higher clock rate due to the differences in the DSP slice multiplier design.

    Due to the small size, low latency and high throughput, the presented floating-point division unit is suitable for high performance embedded systems and can be integrated into accelerators or be used as a stand-alone accelerator.

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    Savas2017Efficient
  • 367.
    Savas, Süleyman
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Raase, Sebastian
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Gebrewahid, Essayas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nordström, Tomas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Dataflow Implementation of QR Decomposition on a Manycore2016In: MES '16: Proceedings of the Third ACM International Workshop on Many-core Embedded Systems, New York, NY: ACM Press, 2016, p. 26-30Conference paper (Refereed)
    Abstract [en]

    While parallel computer architectures have become mainstream, application development on them is still challenging. There is a need for new tools, languages and programming models. Additionally, there is a lack of knowledge about the performance of parallel approaches of basic but important operations, such as the QR decomposition of a matrix, on current commercial manycore architectures.

    This paper evaluates a high level dataflow language (CAL), a source-to-source compiler (Cal2Many) and three QR decomposition algorithms (Givens Rotations, Householder and Gram-Schmidt). The algorithms are implemented both in CAL and hand-optimized C languages, executed on Adapteva's Epiphany manycore architecture and evaluated with respect to performance, scalability and development effort.

    The performance of the CAL (generated C) implementations gets as good as 2\% slower than the hand-written versions. They require an average of 25\% fewer lines of source code without significantly increasing the binary size. Development effort is reduced and debugging is significantly simplified. The implementations executed on Epiphany cores outperform the GNU scientific library on the host ARM processor of the Parallella board by up to 30x. © 2016 Copyright held by the owner/author(s).

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  • 368.
    Savas, Süleyman
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nordström, Tomas
    RISE Research Institutes of Sweden, Gothenburg, Sweden.
    A Configurable Two Dimensional Mesh Network-on-Chip Implementation in Chisel2019Other (Other academic)
    Abstract [en]

    On-chip communication plays a significant role in the performance of manycore architectures. Therefore, they require a proper on-chip communication infrastructure that can scale with the number of the cores. As a solution, network-on-chip structures have emerged and are being used.

    This paper presents description of a two dimensional mesh network-on-chip router and a network interface, which are implemented in Chisel to be integrated to the rocket chip generator that generates RISC-V (rocket) cores. The router is implemented in VHDL as well and the two implementations are verified and compared.

    Hardware resource usage and performance of different sized networks are analyzed. The implementations are synthesized for a Xilinx Ultrascale FPGA via Xilinx tools for the hardware resource usage and clock frequency results. The performance results including latency and throughput measurements with different traffic patterns, are collected with cycle accurate emulations. 

    The implementations in Chisel and VHDL do not show a significant difference. Chisel requires around 10% fewer lines of code, however, the difference in the synthesis results is negligible. Our latency result are better than the majority of the other studies. The other results such as hardware usage, clock frequency, and throughput are competitive when compared to the related works.

  • 369.
    Savas, Süleyman
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Department of Computers Science, Lund University, Lund, Sweden.
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nordström, Tomas
    Umeå University, Umeå, Sweden.
    A Framework to Generate Domain-Specific Manycore Architectures from Dataflow Programs2020In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 72, article id 102908Article in journal (Refereed)
    Abstract [en]

    In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures.

    However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method allows generation of manycore architectures with different configurations including core augmentation through instruction extensions and custom accelerators. The method starts from developing applications in a high-level dataflow language and ends by generating synthesizable Verilog code and cycle accurate emulator for the generated architecture.

    We evaluate the design method and the software tools by generating several architectures specialized for two different applications and measure their performance and hardware resource usages. Our results show that the design method can be used to generate specialized manycore architectures targeting applications from different domains. The specialized architectures show at least 3 to 4 times better performance than the general purpose counterparts. In certain cases, replacing general purpose components with specialized components saves hardware resources. Automating the method increases the speed of architecture development and facilitates the design space exploration of manycore architectures. © 2019 The Authors. Published by Elsevier B.V.

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  • 370.
    Savas, Süleyman
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nordström, Tomas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Designing Domain Specific Heterogeneous Manycore Architectures Based on Building Blocks2018Manuscript (preprint) (Other academic)
    Abstract [en]

    Performance and power requirements has pushed computer architectures from single core to manycores. These requirements now continue pushing the manycores with identical cores (homogeneous) to manycores with specialized cores (heterogeneous). However designing heterogeneous manycores is a challenging task due to the complexity of the architectures. We propose an approach for designing domain specific heterogeneous manycore architectures based on building blocks. These blocks are defined as the common computations of the applications within a domain. The objective is to generate heterogeneous architectures by integrating many of these blocks to many simple cores and connect the cores with a networkon-chip. The proposed approach aims to ease the design of heterogeneous manycore architectures and facilitate usage of dark silicon concept. As a case study, we develop an accelerator based on several building blocks, integrate it to a RISC core and synthesize on a Xilinx Ultrascale FPGA. The results show that executing a hot-spot of an application on an accelerator based on building blocks increases the performance by 15x, with room for further improvement. The area usage increases as well, however there are potential optimizations to reduce the area usage. © 2018 by the authors

  • 371.
    Savas, Süleyman
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nordström, Tomas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs2018In: Computers, ISSN 2073-431X, Vol. 7, no 2, article id 27Article in journal (Refereed)
    Abstract [en]

    The last ten years have seen performance and power requirements pushing computer architectures using only a single core towards so-called manycore systems with hundreds of cores on a single chip. To further increase performance and energy efficiency, we are now seeing the development of heterogeneous architectures with specialized and accelerated cores. However, designing these heterogeneous systems is a challenging task due to their inherent complexity. We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores. These hardware accelerators were determined based on their common use among applications within a certain domain.The objective was to generate heterogeneous architectures by integrating many of these accelerated cores and connecting them with a network-on-chip. The proposed approach aimed to ease the design of heterogeneous manycore architectures—and, consequently, exploration of the design space—by automating the design steps. To evaluate our approach, we enhanced our software tool chain with a tool that can generate accelerated cores from dataflow programs. This new tool chain was evaluated with the aid of two use cases: radar signal processing and mobile baseband processing. We could achieve an approximately 4x improvement in performance, while executing complete applications on the augmented cores with a small impact (2.5–13%) on area usage. The generated accelerators are competitive, achieving more than 90% of the performance of hand-written implementations.

  • 372.
    Savas, Süleyman
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Yassin, Atwa
    Halmstad University, School of Information Technology.
    Nordström, Tomas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit2019In: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE conference proceedings, 2019, p. 621-626Conference paper (Refereed)
    Abstract [en]

    This paper proposes a novel method for performing square root operation on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is implemented using Harmonized Parabolic Synthesis. It is implemented with and without pipeline stages individually and synthesized for two different Xilinx FPGA boards.

    The implementations show better resource usage and latency results when compared to other similar works including Xilinx intellectual property (IP) that uses the CORDIC method. Any method calculating the square root will make approximation errors. Unless these errors are distributed evenly around zero, they can accumulate and give a biased result. An attractive feature of the proposed method is the fact that it distributes the errors evenly around zero, in contrast to CORDIC for instance.

    Due to the small size, low latency, high throughput, and good error properties, the presented floating-point square root unit is suitable for high performance embedded systems. It can be integrated into a processor’s floating point unit or be used as astand-alone accelerator. © 2019 IEEE.

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  • 373.
    Shao, Caixing
    et al.
    School of Communication & Information Engineering, University of Electronic Science & Technology of China, Chengdu, China.
    Leng, Supeng
    School of Communication & Information Engineering, University of Electronic Science & Technology of China, Chengdu, China.
    Fan, Bo
    School of Communication & Information Engineering, University of Electronic Science & Technology of China, Chengdu, China.
    Zhang, Yan
    Simula Research Laboratory, Oslo, Norway.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Connectivity-aware Medium Access Control in Platoon-based Vehicular Ad Hoc Networks2015In: 2015 IEEE International Conference on Communications (ICC), Piscataway , NJ: IEEE Press, 2015, p. 3305-3310Conference paper (Refereed)
    Abstract [en]

    Because of the space and time dynamics of moving vehicles, network connectivity is an important performance metric to affect packet delivery in Vehicular Ad Hoc Networks (VANETs). Grouping vehicles into platoons in VANETs can improve road safety, change the network connectivity, and even reduce channel access collisions. Unfortunately, network connectivity is often ignored in the design of exiting MAC protocols for VANETs. In this paper, we analyze the connectivity probability and present a connectivity-aware Medium Access Control (MAC) protocol for platoon-based VANETs. A multi-priority Markov model is presented to derive the relationship between the connectivity probability and the system saturated throughput. Based on variable traffic status and network connectivity, a multi-channel reservation scheme is adopted to dynamically adjust the length of the Control CHannel (CCH) interval and the Service CHannel (SCH) interval for the improvement of the system performance, in terms of network throughput and the priority packet transmission opportunities for platoons. As a result, some important observations to the design and analysis of such communication systems are provided. © 2015 IEEE

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  • 374.
    Shao, Caixing
    et al.
    University of Electronic Science and Technology of China, Chengdu, China.
    Leng, Supeng
    University of Electronic Science and Technology of China, Chengdu, China.
    Zhang, Yan
    Simula Research Laboratory Oslo, Oslo, Norway.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Analysis of connectivity probability in platoon-based Vehicular Ad Hoc Networks2014In: 2014 International Wireless Communications and Mobile Computing Conference (IWCMC 2014), Piscataway, NJ: IEEE Press, 2014, p. 706-711Conference paper (Refereed)
    Abstract [en]

    Vehicular Ad Hoc Networks (VANETs) can provide safety and non-safety related applications and services to improve the passenger safety and comfort. Due to the space and time dynamics of moving vehicles, network connectivity is an important performance metric to indicate the quality of the network and the user's satisfaction. Grouping vehicles into platoons in the highway can improve road safety, reduce fuel consumption, and decrease traffic congestion. In this paper, we study the connectivity characteristic of platoon-based VANETs. The connectivity probabilities are analyzed for the Vehicle-To-Vehicle (V2V) and Vehicle-To-Infrastructure (V2I) communication scenarios. The relationships between the connectivity probability and the key parameters are investigated, including the traffic density, the coverage of the ordinary vehicle, the coverage of the platoon, the coverage of the Road Side Unit (RSU), the distance between two adjacent RSUs and the ratio of the platoon in the VANET. The results can help the transport system designer to control the traffic on the highway to satisfy the connectivity requirement. Analysis results show that the connectivity probability can be significantly improved when there are platoons in a network. © 2014 IEEE.

  • 375.
    Shao, Caixing
    et al.
    University of Electronic Science and Technology of China, Chengdu, China & College of Computer Science and Technology, Southwest University for Nationalities, Chengdu, China.
    Leng, Supeng
    University of Electronic Science and Technology of China, Chengdu, China.
    Zhang, Yan
    Simula Research Laboratory, Lysaker, Norway & University of Oslo, Oslo, Norway.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Performance Analysis of Connectivity Probability and Connectivity-aware MAC Protocol Design for Platoon-based VANETs2015In: IEEE Transactions on Vehicular Technology, ISSN 0018-9545, E-ISSN 1939-9359, Vol. 64, no 12, p. 5596-5609Article in journal (Refereed)
    Abstract [en]

    Vehicular Ad Hoc Networks (VANETs) can provide safety and non-safety applications to improve the passenger safety and comfort. Grouping vehicles into platoons in VANETs can improve road safety and reduce fuel consumption. It is critical to design an efficient Medium Access Control (MAC) protocol for Platoon-based VANETs. Moreover, because of the space and time dynamics of moving vehicles, network connectivity is an important performance metric to indicate the quality of the network communications and the satisfaction of users. Unfortunately, network connectivity is often ignored in the design of existing MAC protocols for VANETs. In this paper, we study the connectivity characteristics and present a connectivity-aware MAC protocol for platoon-based VANETs. The connectivity probabilities are analyzed for the Vehicle-to-Vehicle (V2V) and Vehicle-to-Infrastructure (V2I) communication scenarios in oneway and two-way VANETs, respectively. A multi-priority Markov model is presented to derive the relationship between the connectivity probability and the system throughput. Based on variable traffic status and network connectivity, a multi-channel reservation scheme is adopted to dynamically adjust the length of the Control CHannel (CCH) interval and the Service CHannel (SCH) interval for the improvement of the system throughput. Analysis and simulation results show that the throughput increases with the connectivity probability. However, with further increase of the connectivity probability, the throughput will decrease due to numerous channel contention. © Copyright 2015 IEEE

  • 376.
    Sikora, Axel
    et al.
    Offenburg University of Applied Sciences, Offenburg, Germany.
    Berbineau, MarionIFSTTAR, Villeneuve d’Ascq, France.Vinel, AlexeyTampere University of Technology, Tampere, Finland.Jonsson, MagnusHalmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).Pirovano, AlainEcole Nationale de l’Aviation, Toulouse, France.Aguado, MarinaUniversity of the Basque Country, Bilbao, Spain.
    Communication Technologies for Vehicles: 6th International Workshop, Nets4Cars/Nets4Trains/Nets4Aircraft 2014: Offenburg, Germany, May 6-7, 2014, Proceedings2014Conference proceedings (editor) (Refereed)
  • 377.
    Singh, Prabhjot
    et al.
    Computer Science and Engineering Department, Chandigarh University, Mohali (Punjab), India.
    Singh Bali, Rasmeet
    Computer Science and Engineering Department, Chandigarh University, Mohali (Punjab), India.
    Kumar, Neeraj
    Computer Sciene and Engineering Department, Thapar University, Patiala (Punjab), India.
    Kumar Das, Ashok
    Center for Security, Theory and Algorithmic Research, International Institute of Information Technology, Hyderabad, India.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Yang, Laurence T.
    Department of Computer Science, St. Francis Xavier University, Antigonish, NS, Canada.
    Secure Healthcare Data Dissemination Using Vehicle Relay Networks2018In: IEEE Internet of Things Journal, ISSN 2327-4662, Vol. 5, no 5, p. 3733-3746Article in journal (Refereed)
    Abstract [en]

    In the recent years, vehicular adhoc networks (VANETs) can be an attractive choice for collecting and transferring the healthcare data of the passengers to the remote healthcare centers. In VANETs, some of the intermediate nodes may act as relay nodes in which case, these networks are called as vehicular relay networks (VRNs). However, the transmitted information in VRNs can be captured by intruders during transmission. Moreover, an attacker can launch selective forwarding, blackhole and sinkhole attacks in the network, which may in turn degrade the network performance parameters like high end-to-end delay, low packet delivery ratio and network throughput. Hence, to address these issues, a secure data dissemination scheme using VRNs is proposed. In the proposed scheme, firstly, a secure vehicular medical relay network system is designed for the users belonging to disconnected rural areas. The collected information is filtered at zonal levels before transmission to a nearby road side units (RSUs), which further pass it to the incoming vehicles. Secondly, a secure passenger health monitoring network is designed which continuously monitors health services of the passengers traveling in different vehicles. The information collected through small body sensors installed in the vehicles act as data sets that is forwarded to the on-board monitoring unit within the vehicle. This collected data is then transmitted to centralized healthcare centers for processing by using VRNs. Lastly, a strong Elliptic Curve Cryptography (ECC)-based cryptographic solution is designed for secure communication among different vehicles. The performance of the proposed scheme is evaluated in various network scenarios with respect to different selected parameters, such as throughput, network delay, packet delivery ratio, jitter, transmission and computation overheads, and key distribution overhead. The obtained results indicate that the proposed scheme provides improvement of 52% in average delay and 5% in packet delivery ratio. This further indicates effective message delivery even with high mobility of the vehicles. © 2018 IEEE

  • 378.
    Song, Liumeng
    et al.
    Queen Mary University of London, London, United Kingdom.
    Chai, Kok Keong
    Queen Mary University of London, London, United Kingdom.
    Chen, Yue
    Queen Mary University of London, London, United Kingdom.
    Schormans, John
    Queen Mary University of London, London, United Kingdom.
    Loo, Jonathan
    University of West London, London, United Kingdom.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    QoS-Aware Energy-Efficient Cooperative Scheme for Cluster-Based IoT Systems2017In: IEEE Systems Journal, ISSN 1932-8184, E-ISSN 1937-9234, Vol. 11, no 3, p. 1447-1455Article in journal (Refereed)
    Abstract [en]

    The Internet of Things (IoT) technology with huge number of power-constrained devices has been heralded to improve the operational efficiency of many industrial applications. It is vital to reduce the energy consumption of each device; however, this could also degrade the quality of service (QoS) provisioning. In this paper, we study the problem of how to achieve the tradeoff between the QoS provisioning and the energy efficiency for the industrial IoT systems. We first formulate the multiobjective optimization problem to achieve the objective of balancing the outage performance and the network lifetime. Then, we propose to combine the quantum particle swarm optimization (QPSO) with the improved nondominated sorting genetic algorithm (NSGA-II) to obtain the Pareto-optimal front. In particular, NSGA-II is applied to solve the formulated multiobjective optimization problem, and the QPSO algorithm is used to obtain the optimum cooperative coalition. The simulation results suggest that the proposed algorithm can achieve the tradeoff between the energy efficiency and the QoS provisioning by sacrificing about 10% network lifetime but improving about 15% outage performance. © 2017 IEEE

  • 379.
    Stranne, Frida
    et al.
    Halmstad University, School of Education, Humanities and Social Science, Research on Education and Learning within the Department of Teacher Education (FULL).
    Bilstrup, Urban
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ewertsson, Lena
    Halmstad University, School of Education, Humanities and Social Science, Center for Social Analysis (CESAM).
    Behind the Mask – Attribution of antagonists in cyberspace and its implications on international conflicts and security issues2015Conference paper (Refereed)
    Abstract [en]

    Cyber systems and critical infrastructure are changing the dynamics of international conflicts, security issues, and challenge traditional ways of understanding warfare. Early warning and attribution of who is accountable for a cyber-attack and what is the intention with the attack is crucial information. To be able to efficiently response to a cyber-antagonist the measure of response must be decided at network speed, which is far beyond what is possible with traditional attribution methods. The ongoing “cyber arm raze” push towards the development and use of autonomous cyber response systems. An autonomous cyber response would most probably use the complexity of attack vector as a tool for attribution, not considering the identity of the antagonist for deciding the measure of response. This will challenge traditional ways of understanding conflict, war, and how nation states handle different kinds of aggressions. This leads to a new kind of deterrence increasing the need to theorize cyber conflicts, as well as empirically study how different actors are acting and reacting in relation to this new threat. This paper initiates the discourse on the implications of the use of autonomous cyber response systems for the international system/relations.

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  • 380.
    Svensson, Bertil
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ericsson, Per M.
    Saab AB (EDS), Gothenburg, Sweden.
    Åhlander, Anders
    Saab AB (EDS), Gothenburg, Sweden.
    Hoang Bengtsson, Hoai
    Viktoria Swedish ICT, Gothenburg, Sweden.
    Bengtsson, Jerker
    Saab AB (EDS), Gothenburg, Sweden.
    Gaspes, Veronica
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nordström, Tomas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Running Leap for Embedded Signal Processing to Future Parallel Platforms2014In: WISE'14: Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering, New York, NY: Association for Computing Machinery (ACM), 2014, p. 35-42Conference paper (Refereed)
    Abstract [en]

    This paper highlights the collaboration between industry and academia in research. It describes more than two decades of intensive development and research of new hardware and software platforms to support innovative, high-performance sensor systems with extremely high demands on embedded signal processing capability. The joint research can be seen as the run before a necessary jump to a new kind of computational platform based on parallelism. The collaboration has had several phases, starting with a focus on hardware, then on efficiency, later on software development, and finally on taking the jump and understanding the expected future. In the first part of the paper, these phases and their respective challenges and results are described. Then, in the second part, we reflect upon the motivation for collaboration between company and university, the roles of the partners, the experiences gained and the long-term effects on both sides. Copyright © 2014 ACM.

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  • 381.
    Sámano-Robles, Ramiro
    et al.
    Research Centre in Real-time and Embedded Computing Systems, Porto, Portugal.
    Nordström, Tomas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Santonja, Salvador
    Instituto Tecnologico de Informatica (ITI), Valencia, Spain.
    Rom, Werner
    VIRTUAL VEHICLE Research Centre, Graz, Austria.
    Tovar, Eduardo
    Research Centre in Real-time and Embedded Computing Systems, Porto, Portugal.
    The DEWI High-Level Architecture: Guidelines for Structuring Wireless Sensor Networks in Industrial Applications2016In: 2016 Eleventh International Conference on Digital Information Management (ICDIM), New York: IEEE, 2016, p. 274-280Conference paper (Refereed)
    Abstract [en]

    This paper presents the high-level architecture (HLA) of the research project DEWI (dependable embedded wireless infrastructure). The objective of this HLA is to serve as a reference for the development of industrial wireless sensor and actuator networks (WSANs) based on the concept of the DEWI Bubble. The DEWI Bubble is defined here as a high-level abstraction of an industrial WSAN with enhanced interoperability (via standardized interfaces), technology reusability, and cross-domain development. This paper details the design criteria used to define the HLA and the organization of the infrastructure internal and external to the DEWI Bubble. The description includes the different perspectives, models or views of the architecture: the entity model, the layered model, and the functional view model (including an overview of interfaces). The HLA constitutes an extension of the ISO/IEC SNRA (sensor network reference architecture) towards the support of industrial applications. To improve interoperability with existing approaches the DEWI HLA also reuses some features from other standardized technologies and architectures. The HLA will allow networks with different industrial sensor technologies to exchange information between them or with external clients via standard interfaces, thus providing a consolidated access to sensor information of different domains. This is an important aspect for smart city applications, Big Data and internet-of-things (IoT). © Copyright 2016 IEEE

  • 382.
    Taha, Walid
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Univ Houston, Houston, TX 77004 USA & Chalmers, Gothenburg, Sweden.;Yale, New Haven, CT USA.;Rice Univ, Houston, TX 77251 USA.;Schlumberger, Sugar Land, TX USA.;Lucent Bell Labs, Murray Hill, NJ USA..
    Rigorous simulation2018In: / [ed] Salem, A., Abbas, H. M., Elkharashi, M. W., Eldin, A. M. B., Taher, M., Zaki, A. M., Institute of Electrical and Electronics Engineers (IEEE), 2018, p. XXIII-XXIVConference paper (Refereed)
  • 383.
    Taha, Walid
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Brauner, Paul
    Rice University Houston, TX, USA.
    Cartwright, Robert
    Rice University Houston, TX, USA.
    Gaspes, Veronica
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ames, Aaron
    University of Texas A&M College Station, TX, USA.
    Chapoutot, Alexandre
    ENSTA ParisTech Paris, France.
    A Core Language for Executable Models of Cyber Physical Systems: work in progress report2011Conference paper (Refereed)
    Abstract [en]

    Recently we showed that an expressive class of mathemat-ical equations can be automatically translated into simula-tion codes. Focusing on the expressivity of equations oncontinuous functions, this work considered only minimal in-teraction with discrete behaviors and only a static numberof statically connected components. However, the interac-tion between continuous and hybrid components in manycyber physical domains is highly coupled, and such systemsare often highly dynamic in both respects. This paper givesan overview of a proposed core language for capturing ex-ecutable hybrid models of highly dynamic cyber physicalsystems.

  • 384.
    Taha, Walid
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Brauner, Paul
    Rice University, Houston, TX, USA.
    Zeng, Yingfu
    Rice University, Houston, TX, USA.
    Cartwright, Robert
    Rice University, Houston, TX, USA.
    Gaspes, Veronica
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ames, Aaron
    University of Texas A&M, College Station, TX, USA.
    Chapoutot, Alexandre
    ENSTA ParisTech, Paris, France.
    A Core Language for Executable Models of Cyber-Physical Systems (Preliminary Report)2012Conference paper (Refereed)
    Abstract [en]

    Recently we showed that an expressive class of mathematical equations can be automatically translated into simulation codes. By focusing on the expressivity of equations formed from continuous functions, this work did not accommodate a wide range of discrete behaviors or a dynamic collection of components. However, the interaction between continuous and hybrid components in many cyber-physical domains is highly coupled, and such systems are often highly dynamic in both respects. This paper gives an overview of a proposed core language for capturing executable hybrid models of highly dynamic cyber-physical systems. © 2012 IEEE.

  • 385.
    Taha, Walid
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Computer Science, Rice University, Houston, USA.
    Cartwright, Robert
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS). Computer Science, Rice University, Houston, USA.
    Some Challenges for Model-Based Simulation2013In: Proceedings of the 4th Analytic Virtual Integration of Cyber-Physical Systems Workshop: December 3, Vancouver, Canada / [ed] David Broman & Gabor Karsai, Linköping: Linköping University Electronic Press, 2013, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Comprehensive analytical modeling and simulation of cyber-physical systems is an integral part of the process that brings novel designs and products to life. But the effort needed to go from analytical models to running simulation code can impede or derail this process. Our thesisis that this process is amenable to automation, and that automating it will accelerate the pace of innovation. This paper reviews some basic concepts that we found interesting or thought-provoking, and articulates some questions that may help prove or disprove this thesis. While based on ideas drawn from different disciplines, we observe that all these questions pertain in a profound way to how we can reason and compute with real numbers.

  • 386.
    Taha, Walid
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Cartwright, Robert
    Rice University, Houston, Texas, USA.
    The Trouble with Real Numbers2011In: INFORMATIK 2011: Informatik schafft Communities: Proceedings der 41. GI-Jahrestagun: 4.-7. Oktober 2011: Berlin / [ed] Hans-Ulrich Heiß, Peter Pepper, Holger Schlingloff, Jörg Schneider, Bonn: Bonner Köllen Verlag , 2011, p. 325-Conference paper (Other academic)
  • 387.
    Taha, Walid
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Rice University, Houston, USA.
    Cartwright, Robert
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Rice University, Houston, USA.
    Philippsen, Roland
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), CAISR - Center for Applied Intelligent Systems Research.
    Zeng, Yingfu
    Rice University, Houston, USA.
    A First Course on Cyber Physical Systems2013Conference paper (Refereed)
    Abstract [en]

    Effective and creative CPS development requires expertise in disparate fields that have traditionally been taught in distinct disciplines. At the same time, students seeking a CPS education generally come from diverse educational backgrounds. In this paper we report on our recent experience developing and teaching a course on CPS. The course can be seen as a detailed proposal focused on three three key questions: What are the core elements of CPS? How can these core concepts be integrated in the CPS design process? What types of modeling tools can assist in the design of cyber-physical systems? Experience from the first two offerings of the course is promising, and we discuss the lessons learned. All materials including lecture notes and software used for the course are openly available online.

  • 388.
    Taha, Walid
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Rice University, Houston, TX, USA.
    Cartwright, Robert
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Rice University, Houston, TX, USA.
    Philippsen, Roland
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), CAISR - Center for Applied Intelligent Systems Research.
    Zeng, Yingfu
    Rice University, Houston, TX, USA.
    Developing A First Course on Cyber-Physical Systems2014In: Proceedings of the WESE'14: Workshop on Embedded and Cyber-Physical Systems Education / [ed] Martin Edin Grimheden, New York, NY: ACM Press, 2014, article id 6Conference paper (Refereed)
    Abstract [en]

    Effective and creative cyber-physical systems (CPS) development requires expertise in disparate fields that have traditionally been taught in several distinct disciplines. At the same time, students seeking a CPS education generally come from diverse educational backgrounds. In this paper, we report on our recent experience developing and teaching a course on CPS. The course addresses the following three questions: What are the core elements of CPS? How should these core concepts be integrated in the CPS design process? What types of modeling tools can assist in the design of cyber-physical systems? Our experience with the first three offerings of the course has been positive overall. We also discuss the lessons we learned from some issues that were not handled well. All material including lecture notes and software used for the course are openly available online. © 2014 ACM.

  • 389.
    Taha, Walid
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Duracz, Adam
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Zeng, Yingfu
    Rice University, Houston TX, USA.
    Atkinson, Kevin
    Rice University, Houston TX, USA.
    Bartha, Ferenc Ágoston
    Rice University, Houston TX, USA.
    Brauner, Paul
    Rice University, Houston TX, USA.
    Duracz, Jan
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Xu, Fei
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Cartwright, Robert
    Rice University, Houston TX, USA.
    Konečný, Michal
    Computer Science Group, Aston University, Birmingham, United Kingdom.
    Moggi, Eugenio
    University of Genova, Genoa, Italy.
    Masood, Jawad
    Rice University, Houston TX, USA.
    Andreasson, Björn Pererik
    Halmstad University, School of Information Technology.
    Inoue, Jun
    Rice University, Houston TX, USA.
    Sant'Anna, Anita
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), CAISR - Center for Applied Intelligent Systems Research.
    Philippsen, Roland
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), CAISR - Center for Applied Intelligent Systems Research.
    Chapoutot, Alexandre
    ENSTA ParisTech - U2IS, Paris, France.
    O'Malley, Marcia
    Department of Mechanical Engineering, Rice University, Houston TX, USA.
    Ames, Aaron
    School of Mechanical Eng., Georgia Institute of Technology, Atlanta GA, USA.
    Gaspes, Veronica
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Hvatum, Lise
    Schlumberger, Houston TX, USA.
    Mehta, Shyam
    Schlumberger, Houston TX, USA.
    Eriksson, Henrik
    Dependable Systems, SP Technical Research Institute of Sweden, Borås, Sweden.
    Grante, Christian
    AB Volvo, Gothenburg, Sweden.
    Acumen: An Open-source Testbed for Cyber-Physical Systems Research2016In: Internet of Things. IoT Infrastructures: Second International Summit, IoT 360° 2015, Rome, Italy, October 27-29, 2015. Revised Selected Papers, Part I / [ed] Benny Mandler, Johann Marquez-Barja, Miguel Elias Mitre Campista, Dagmar Cagáňová, Hakima Chaouchi, Sherali Zeadally, Mohamad Badra, Stefano Giordano, Maria Fazio, Andrey Somov & Radu-Laurentiu Vieriu, Heidelberg: Springer, 2016, Vol. 169, p. 118-130Conference paper (Refereed)
    Abstract [en]

    Developing Cyber-Physical Systems requires methods and tools to support simulation and verification of hybrid (both continuous and discrete) models. The Acumen modeling and simulation language is an open source testbed for exploring the design space of what rigorous-but-practical next-generation tools can deliver to developers of Cyber-Physical Systems. Like verification tools, a design goal for Acumen is to provide rigorous results. Like simulation tools, it aims to be intuitive, practical, and scalable. However, it is far from evident whether these two goals can be achieved simultaneously.

    This paper explains the primary design goals for Acumen, the core challenges that must be addressed in order to achieve these goals, the "agile research method" taken by the project, the steps taken to realize these goals, the key lessons learned, and the emerging language design. © ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 2016.

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  • 390.
    Taha, Walid
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Gaspes, Veronica
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Page, Rex
    University of Oklahoma, Norman, OK, USA.
    Accurate Programming: Thinking about programs in terms of properties2011In: Proceedings IFIP Working Conference on Domain-Specific Languages / [ed] Olivier Danvy & Chung-chieh Shan, Open Publishing Association , 2011, Vol. 66, p. 236-260Conference paper (Refereed)
    Abstract [en]

    Accurate programming is a practical approach to producing high quality programs. It combines ideas from test-automation, test-driven development, agile programming, and other state of the art software development methods. In addition to building on approaches that have proven effective in practice, it emphasizes concepts that help programmers sharpen their understanding of both the problems they are solving and the solutions they come up with. This is achieved by encouraging programmers to think about programs in terms of properties.

    Download full text (pdf)
    fulltext
  • 391.
    Taha, Walid
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Rice University, Houston, Texas, United States.
    Hedström, Lars-Göran
    Halmstad University.
    Xu, Fei
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Duracz, Adam
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Bartha, Ferenc A.
    Rice University, Houston, Texas, United States.
    Zeng, Yingfu
    Rice University, Houston, Texas, United States.
    David, Jennifer
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Gunjan, Gaurav
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Flipping a First Course on Cyber-Physical Systems – An Experience Report2016In: Proceedings Of The 2016 Workshop On Embedded And Cyber-Physical Systems Education (Wese), New York: ACM Press, 2016Conference paper (Refereed)
    Abstract [en]

    The flipped classroom format involves swapping activities traditionally performed inside and outside the classroom. The expected effects from this swap include increased student engagement and peer-to-peer interaction in the classroom, as well as more flexible access to learning materials. Key criteria for successful outcomes from these effects include improved test scores and enhanced student satisfaction. Unfortunately, while many researchers have reported positive outcomes from the approach, some instructors can still encounter difficulties in reproducing this success.

    In this paper we report our experiences with flipping a first course on Cyber-Physical Systems at Halmstad University. The course is required for a Masters level program and is available as an elective for undergraduates. The focus of this report is on three separate editions of the course taught over three years. In the first year, lectures were recorded. In the second, the same instructor taught the course using the flipped format. In the third, new instructors taught it using the flipped classroom format.

    Our experience suggests that flipping a classroom can lead to improved student performance and satisfaction from the first edition. It can also enable new instructors to take over the course and perform at a level comparable to an experienced instructor. On the other hand, it also suggests that the format may require more effort to prepare for, and to teach, than the traditional format, and that a higher level of attention to detail is needed to execute it with positive outcomes. Thus, the format can be demanding for instructors. It is also the case that not all students preferred this format.

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    fulltext
  • 392.
    Taha, Walid
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Philippsen, Roland
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Intelligent systems (IS-lab).
    Modeling Basic Aspects of Cyber-Physical Systems2012In: 3rd International Workshop on Domain-Specific Languages and models for ROBotic systems (DSLRob-12), 2012Conference paper (Refereed)
    Abstract [en]

    Designing novel cyber-physical systems entails significant, costly physical experimentation. Simulation tools can enable the virtualization of experiments. Unfortunately, current tools have shortcomings that limit their utility for virtual experimentation. Language research can be especially helpful in addressing many of these problems. As a first step in this direction, we consider the question of determining what language features are needed to model cyber-physical systems. Using a series of elementary examples of cyber-physical systems, we reflect on the extent to which a small, experimental domain-specific formalism called Acumen suffices for this purpose.

    Download full text (pdf)
    taha-philippsen--dslrob2012.pdf
  • 393.
    Taha, Walid
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Zeng, Yingfu
    Rice University, Houston, TX, USA.
    Duracz, Adam
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Xu, Fei
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Atkinson, Kevin
    Rice University, Houston, TX, USA.
    Brauner, Paul
    Rice University, Houston, TX, USA.
    Cartwright, Robert
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Rice University, Houston, TX, USA.
    Philippsen, Roland
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), CAISR - Center for Applied Intelligent Systems Research.
    Developing a first course on cyber-physical systems2016In: ACM SIGBED Review, E-ISSN 1551-3688, Vol. 14, no 1, p. 44-52Article in journal (Refereed)
    Abstract [en]

    Effective and creative Cyber-Physical Systems (CPS) development requires expertise in disparate fields that have traditionally been taught in several distinct disciplines. At the same time, students seeking a CPS education generally come from diverse educational backgrounds. In this paper, we report on our recent experience of developing and teaching a course on CPS. The course addresses the following three questions: What are the core elements of CPS? How should these core concepts be integrated in the CPS design process? What types of modeling tools can assist in the design of Cyber-Physical Systems? Our experience with the first four offerings of the course has been positive overall. We also discuss the lessons we learned from some issues that were not handled well. All material including lecture notes and software used for the course are openly available online.

  • 394.
    Tahir, Madiha
    et al.
    Mohammad Ali Jinnah University, Islamabad, Pakistan.
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). TeleSehat Private Limited, Islamabad, Pakistan.
    Qadir, Muhammad Abdul
    Mohammad Ali Jinnah University, Islamabad, Pakistan.
    Enhancing the HEVC Video Analyzer for Medical Diagnostic Videos2015In: 2015 12th International Conference on High-capacity Optical Networks and Enabling/Emerging Technologies (HONET), [S.l.]: IEEE , 2015, p. 65-69, article id 7395417Conference paper (Refereed)
    Abstract [en]

    Video analyzers are employed to perform an in depth analysis of coding decisions undertaken during the execution of a video codec. Medical diagnostic videos, which are typically dealt with in telemedicine scenarios need careful examination to incorporate the most optimum coding decisions. This paper deals with the enhancement of an open-source video stream analyzer to facilitate codec development tailored for medical diagnostic videos. The proposed extensions include visual representation of quantitative information for the bit count used at CTU level, as well as displaying the different mode decisions adopted in the case of merge mode, prediction mode, and intra mode. We have incorporated the said extensions in HEVC analyzer and validated the approach by using test video sequences for Ultrasound, Eye, and Skin examination. © 2015 IEEE.

  • 395.
    Taromirad, Masoumeh
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Mousavi, Mohammad Reza
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Gray-Box Conformance Testing for Symbolic Reactive State Machines2017In: Fundamentals of Software Engineering: 7th International Conference, FSEN 2017, Tehran, Iran, April 26–28, 2017, Revised Selected Papers / [ed] Mehdi Dastani & Marjan Sirjani, Heidelberg: Springer Berlin/Heidelberg, 2017, p. 228-243Conference paper (Refereed)
    Abstract [en]

    Model-based testing (MBT) is typically a black-box testing technique. Therefore, generated test suites may leave some untested gaps in a given implementation under test (IUT). We propose an approach to use the structural and behavioural information exploited from the implementation domain to generate effective and efficient test suites. Our approach considers both specification models and implementation models, and generates an enriched test model which is used to automatically generate test suites. We show that the proposed approach is sound and exhaustive and cover both the specification and the implementation. We examine the applicability and the effectiveness of our approach by applying it to a well-known example from the railway domain. © 2017, IFIP International Federation for Information Processing.

  • 396.
    Thunberg, Johan
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Lyamin, Nikita
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Sjöberg, Katrin
    Scania, Södertälje, Sweden.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Department of Electrical Engineering, Western Norway University of Applied Sciences, Bergen, Norway.
    Vehicle-to-Vehicle Communications for Platooning: Safety Analysis2019In: IEEE Networking Letters, ISSN 2576-3156, Vol. 1, no 4, p. 168-172Article in journal (Refereed)
    Abstract [en]

    Vehicle-to-vehicle (V2V) communication is the key technology enabling platooning. This paper proposes an analytical framework that combines the characteristics of V2V communication (packet loss probabilities and packet transmission delays) with the physical mobility characteristics of vehicles (speed, distance between vehicles and their brake capacities). First, we present the feasible region of communications delays which guarantees safe emergency braking in platooning scenarios. Second, we derive a bound on the probability of safe braking. The presented framework is applied to understand the performance of the state-of-the-art V2V communication protocol for platooning.

  • 397.
    Thunberg, Johan
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Markdahl, Johan
    Luxembourg Centre for Systems Biomedicine, University of Luxembourg, Luxembourg.
    Goncalves, Jorge
    Luxembourg Centre for Systems Biomedicine, University of Luxembourg, Luxembourg.
    Dynamic controllers for column synchronization of rotation matrices: A QR-factorization approach2018In: Automatica, ISSN 0005-1098, E-ISSN 1873-2836, Vol. 93, p. 20-25Article in journal (Refereed)
    Abstract [en]

    In the multi-agent systems setting, this paper addresses continuous-time distributed synchronization of columns of rotation matrices. More precisely, k specific columns shall be synchronized and only the corresponding k columns of the relative rotations between the agents are assumed to be available for the control design. When one specific column is considered, the problem is equivalent to synchronization on the (d−1)-dimensional unit sphere and when all the columns are considered, the problem is equivalent to synchronization on SO(d). We design dynamic control laws for these synchronization problems. The control laws are based on the introduction of auxiliary variables in combination with a QR-factorization approach. The benefit of this QR-factorization approach is that we can decouple the dynamics for the k columns from the remaining d−k ones. Under the control scheme, the closed loop system achieves almost global convergence to synchronization for quasi-strong interaction graph topologies.

  • 398.
    Tirkkonen, Olav
    et al.
    Aalto University, Helsinki, Finland & Cornell University, New York, NY, USA.
    Li, Zexian
    Nokia Bell Labs, Espoo, Finland.
    Wei, Lu
    University of Michigan, Dearborn, MI, USA.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    On-Off Necklace Codes for Asynchronous Mutual Discovery2017In: 2017 IEEE 28th Annual International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), IEEE, 2017Conference paper (Refereed)
    Abstract [en]

    We consider mutual discovery of asynchronous wireless transceivers with a fixed activity ratio. On-off activity patterns are slotted, and repeat in discovery frames. For discovery it has to be guaranteed that the activity patterns of two transceivers are not overlapping. We design necklace codes determining activity patterns to guarantee discovery within a discovery frame, so that two asynchronous transceivers always have non-overlapping activity patterns. The number of distinct patterns is analyzed as a function of discovery frame length, and on-off activity ratio. As an application example, we consider the discovery problem for vehicle-to-vehicle communication. To guarantee discovery of far-away vehicles, discovery sequences providing processing gain, and necklace coded activity patterns are needed. We find that billions of discovery code identities can be provided with a repetition frequency that is high enough to guarantee a missed discovery probability less than 10−6.

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    fulltext
  • 399.
    Uddman Jansson, Oscar
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Shahanoor, Golam
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), CAISR - Center for Applied Intelligent Systems Research.
    Evaluation of string stability during highway platoon merge2016Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Automated vehicles are considered to be the future solution to reduce

    traffic congestion and to increase road safety. The Adaptive Cruise

    Control (ACC) has been introduced as Advance Driver Assistance System

    (ADAS) to improve road network utilization. However, complex

    traffic situations are still resolved by human drivers. Vehicular communication

    has been introduced to interconnect different nodes in

    the transport system for example vehicles, infrastructure, and vulnerable

    road users. Communication enables improved local awareness of

    the road users and the potential to further improve the performance

    is increased. In this study, a popular ACC algorithm, the notion of

    string stability and the concept of Cooperative Adaptive Cruise Control

    (CACC) are discussed. A new CACC algorithm is proposed focusing

    on maintaining platoon string stability during different traffic

    situations. The performance of the controller is compared with one

    of the most accepted ACC algorithms. The proposed controller was

    implemented in a real world cooperative highway merge scenario.

    The collected data was presented and appraised under three different

    evaluation criteria. The controller has shown low downstream

    error propagation in simulation and in real world experiment it successfully

    maintained string stability during highway platooning and

    merging scenarios.

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    fulltext
  • 400.
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Report on Wireless Vehicular Communications: [VTS News]2012In: IEEE Vehicular Technology Magazine, ISSN 1556-6072, E-ISSN 1556-6080, Vol. 7, no 3, p. 102-106Article in journal (Other academic)
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