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  • 201.
    Zhang, Chi
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Tic-tac-toe game design based on Xilinx FPGA2010Självständigt arbete på grundnivå (kandidatexamen), 15 poäng / 22,5 hpStudentuppsats (Examensarbete)
    Abstract [en]

    This design accomplished Tic-Tac-Toe game on Xilinx Spartan-IIE FPGA platformin VHDL. Firstly, designing the circuits and wiring on experiment board. Secondly,designing the algorithm and programming it in Active-HDL. Thirdly, synthesizingit in Synplicity Synplify Pro and then implementing it in Xilinx ISE developingsuite. Finally download it onto FPGA to run it.

    This design allows two players to play Tic-Tac-Toe game on the experiment board.Pressing the key, the corresponding LED will be light up to represent thechessman. There are two LEDs indicate whose turn next is. If the grid one wantsto place chessman has been taken up, then LCD will alarm it and ask the playerto replace it. The first player who forms 3 chessmen in a row, column or diagonalwins, LCD will display it and the three LEDs in the winning line will blink. If nobody wins after filling the whole chessboard, then LCD displays draw.

  • 202.
    Zheyuan, Liu
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Evaluation of platoon Application Enabled by Contemporary ETSI ITS-G5 Standards2015Självständigt arbete på avancerad nivå (masterexamen), 80 poäng / 120 hpStudentuppsats (Examensarbete)
  • 203.
    Åhlander, Anders
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Efficient parallell architectures for future radar signal processing2007Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    The processing demands on future embedded radar signal processors may stretch to several trillions of floating-point operations per second (TFLOPS). This is an increase of two to three orders of magnitude realtive to the requirements of today. Still, the tight size and power constraints are unchanged. To meet this, new, highly parallel computer systems are needed. The systems should efficiently deliver very high performance as well as being general enough. Another challenge for future signal processors is the requirement for having huge working memories that are accessed in complicated patterns.

    This thesis analyses the challenges of two classes of radar signal processing applications, namely Space-Time Adaptive Processing (STAP), which represents performance-intensive applications, and Synthetic Aperture Radar (SAR) processing, which represents memory-intensive applications. In addition to the actual performance and memory aspects of the applications, the desire for low-effort application development and maintenance is taken into consideration.

    A multiple SIMD architecture is proposed for the STAP calculations. This architecture gives a combination of the high computational density in the SIMD processing modules with the overall flexibility provided on the system level. An embedded signal processing system based on the architecture is shown to be capable of TFLOPS class performance using standard CMOS VLSI technology available in the year 2001. The system is, for the given application domain, considered to have the same generality as commercial off-the-shelf (COTS) hardware, but has several years of time lead over COTS with regard to the computational performance.

    The studied SAR processing is characterized by operating on huge data sets and having varying, non-linear data access paths. For this, algorithm solutions and execution schemes in inerplay with a system parallelization approach are proposed. It is shown that it is possible to obtain efficient memory accesses, despite the omplicated memory access patterns. It is also shown that the computational burden from complex interpolation kernels can be reduced through extensive calculation reuse.

    Efficient engineering of complex applications in this context is discussed. The use of semi-transparent, platform-based development is demonstrated for STAP and SAR, and advocated for obtaining high engineering defficiency and long system sustainability, as well as high performance efficiency.

    The overall conclusion drawn from this work is that a solid knowledge of the application domain and its future requirements, in combination with an understanding of its interaction with computational architectures, potentially enables several years of lead time in the realization of new, advanced signal prodcessing products. The important requirements on programmability and sustainability must also be taken into account in order to achieve a viable signal processing solution.

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