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  • 151.
    He, Debiao
    et al.
    Wuhan University, Wuhan, China.
    Kumar, Neeraj
    Thapar University, Patiala, India.
    Zeadally, Sherali
    University of the District of Columbia, Lexington, Kentucky, USA.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Yang, Laurence T.
    St. Francis Xavier University, Antigonish, Canada.
    Efficient and Privacy-Preserving Data Aggregation Scheme for Smart Grid against Internal Adversaries2017In: IEEE Transactions on Smart Grid, ISSN 1949-3053, E-ISSN 1949-3061, Vol. 8, no 5, p. 2411-2419Article in journal (Refereed)
    Abstract [en]

    Privacy-Preserving Data Aggregation (P2DA) is an important basic building block that can protect consumer’s privacy in the smart grid environment because it could be used to prevent the extraction of the electricity consumption information of a specific consumer. Due to this important function, the P2DA scheme for the smart grid has attracted a lot of attention from both academic and industry researchers who have proposed many P2DA schemes for the smart grid in recent years. However, most of these P2DA schemes are not secure against internal attackers or cannot provide data integrity. Besides, their computation costs are not satisfactory because the bilinear pairing operation or the hash-to-point operation is performed at the smart meter’s side. To address the deficiencies of previous schemes, we propose a new P2DA scheme against internal attackers using Boneh-Goh-Nissim public key cryptography. The proposed P2DA scheme does not use bilinear pairing or hash-to-point operations making it more computationally efficient than previous P2DA schemes. We also show that the proposed P2DA scheme is provably secure and can meet various security requirements. © Copyright 2017 IEEE

  • 152.
    Heimfarth, Tales
    et al.
    Federal University of Lavras, Brazil.
    Freitas, Edison Pignaton de
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Netto, Ivayr Farah
    Federal University of Lavras, Brazil.
    Correia, Luiz H. A.
    Federal University of Lavras, Brazil.
    Pereira, Carlos Eduardo
    Federal University of Rio Grande do Sul, Porto Alegre, Brazil.
    Ferreira, Armando Morado
    Military Institute of Engineering, Rio de Janeiro, Brazil.
    Wagner, Flávio Rech
    Federal University of Rio Grande do Sul, Porto Alegre, Brazil.
    Larsson, Tony
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Enhanced pheromone-based mechanism to coordinate UAVs and WSN nodes on the ground2010In: INFOCOMP Journal of Computer Science, ISSN 1807-4545, E-ISSN 1982-3363, Vol. 9, no 2, p. 75-84Article in journal (Refereed)
  • 153.
    Hertz, Erik
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Lund University, Lund, Sweden.
    Methodologies for Approximation of Unary Functions and Their Implementation in Hardware2016Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Applications in computer graphics, digital signal processing, communication systems, robotics, astrophysics, fluid physics and many other areas have evolved to become very computation intensive. Algorithms are becoming increasingly complex and require higher accuracy in the computations. In addition, software solutions for these applications are in many cases not sufficient in terms of performance. A hardware implementation is therefore needed. A recurring bottleneck in the algorithms is the performance of the approximations of unary functions, such as trigonometric functions, logarithms and the square root, as well as binary functions such as division. The challenge is therefore to develop a methodology for the implementation of approximations of unary functions in hardware that can cope with the growing requirements. The methodology is required to result in fast execution time, low complexity basic operations that are simple to implement in hardware, and – sincemany applications are battery powered – low power consumption. To ensure appropriate performance of the entire computation in which the approximation is a part, the characteristics and distribution of the approximation error are also things that must be possible to manage. The new approximation methodologies presented in this thesis are of the type that aims to reduce the sizes of the look-up tables by the use of auxiliary functions. They are founded on a synthesis of parabolic functions by multiplication – instead of addition, which is the most common. Three approximation methodologies have been developed; the two last being further developments of the first. For some functions, such as roots, inverse and inverse roots, a straightforward solution with an approximation is not manageable. Since these functions are frequent in many computation intensive algorithms, it is necessary to find very efficient implementations of these functions. New methods for this are also presented in this thesis. They are all founded on working in a floating-point format, and, for the roots functions, a change of number base is also used. The transformations not only enable simpler solutions but also increased accuracy, since the approximation algorithm is performed on a mantissa of limited range. Tools for error analysis have been developed as well. The characteristics and distribution of the approximation error in the new methodologies are presented and compared with existing state-of-the-art methods such as CORDIC. The verification and evaluation of the solutions have to a large extent been made as comparative ASIC implementations with other approximation methods, separately or embedded in algorithms. As an example, an implementation of the logarithm made using the third methodology developed, Harmonized Parabolic Synthesis (HPS), is compared with an implementation using the CORDIC algorithm. Both implementations are designed to provide 15-bit resolution. The design implemented using HPS performs 12 times better than the CORDIC implementation in terms of throughput. In terms of energy consumption, the new methodology consumes 96% less. The chip area is 60% smaller than for the CORDIC algorithm. In summary, the new approximation methodologies presented are found to well meet the demanding requirements that exist in this area.

  • 154.
    Hertz, Erik
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Lai, Jingou
    Lund University, Lund, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nilsson, Peter
    Lund University, Lund, Sweden.
    The harmonized parabolic synthesis methodology for function generation in hardwareManuscript (preprint) (Other academic)
    Abstract [en]

    The Harmonized Parabolic Synthesis methodology is a further development of the Parabolic Synthesis methodology for approximation of unary functions such as trigonometric functions, logarithms and the square root, as well as binary functions such as division, in hardware.These functions are extensively used in computer graphics, digital signal processing, communication systems, robotics, astrophysics, fluid physics and many other application areas. For these high-speed applications, software solutions are in many cases not sufficient and a hardware implementation is therefore needed. The Harmonized Parabolic Synthesis methodology has two outstanding advantages: it is parallel, thus reducing the execution time, and it is based on low 2complexity operations, thus is simple to implement in hardware. A notable difference in the Harmonized Parabolic Synthesis methodology compared to many other approximation methodologies is that it is a multiplicative and not an additive methodology. Without harming the favorable distribution of the approximation error presented in earlier described Parabolic Synthesis methodologies it is possible to significantly enhances the performance of the Harmonized Parabolic Synthesis methodology, in terms of reducing chip area, computation delay and power consumption. Furthermore it increases the possibility to tailor the characteristics of the error, which improves the conditions for subsequent calculations. It also extends the set of unary functions that approximations can be performed upon since the possibilities to elaborate with the characteristics and distribution of the error increases. To evaluate the proposed methodology, the fractional part of the logarithm has been implemented and its performance is compared to the Parabolic Synthesis methodology. The comparison is made with 15-bit resolution. The design implemented using the Harmonized Parabolic Synthesis methodology performs 3x better than the Parabolic Synthesis implementation in terms of throughput. In terms of energy consumption, the new methodology consumes 90% less. The chip area is 70% smaller than for the Parabolic Synthesis methodology. In summary, the new technology presented in this paper further increases the advantages of Parabolic Synthesis.

  • 155.
    Hertz, Erik
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Lai, Jingou
    Lund University, Lund, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nilsson, Peter
    Lund University, Lund, Sweden.
    The Harmonized Parabolic Synthesis Methodology for Hardware Efficient Function Generation with Full Error Control2018In: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115, Vol. 90, no 12, p. 1623-1637Article in journal (Refereed)
    Abstract [en]

    The Harmonized Parabolic Synthesis methodology is a further development of the Parabolic Synthesis methodology for approximation of unary functions such as trigonometric functions, logarithms and the square root with moderate accuracy for ASIC implementation. These functions are extensively used in computer graphics, communication systems and many other application areas. For these high-speed applications, software solutions are in many cases not sufficient and a hardware implementation is therefore needed. The Harmonized Parabolic Synthesis methodology has two outstanding advantages: it is parallel, thus reducing the execution time, and it is based on low complexity operations, thus is simple to implement in hardware. A difference compared to other approximation methodologies is that it is a multiplicative and not additive, methodology. Compared to the Parabolic Synthesis methodologies it is possible to significantly enhance the performance in terms of reducing chip area, computation delay and power consumption. Furthermore it increases the possibility to tailor the characteristics of the error, improving conditions for subsequent calculations and the performance in design terms. To evaluate the proposed methodology, the fractional part of the logarithm has been implemented and its performance is compared to the Parabolic Synthesis methodology. The comparison is made with 15-bit resolution. The design implemented using the proposed methodology performs 3x better than the Parabolic Synthesis implementation in terms of throughput. In terms of energy consumption, the new methodology consumes 90% less. The chip area is 70% smaller than for the Parabolic Synthesis methodology. In summary, the new technology further increases the advantages of Parabolic Synthesis. © 2017 The Author(s)

  • 156.
    Hertz, Erik
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nilsson, Peter
    Department of Electrical and Information Technology, Lund University, Lund, Sweden.
    Combining the Parabolic Synthesis Methodology with Second-Degree Interpolation2016In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 42, p. 142-155Article in journal (Refereed)
    Abstract [en]

    The Parabolic Synthesis methodology is an approximation methodology for implementing unary functions, such as trigonometric functions, logarithms and square root, as well as binary functions, such as division, in hardware. Unary functions are extensively used in baseband for wireless/wireline communication, computer graphics, digital signal processing, robotics, astrophysics, fluid physics, games and many other areas. For high-speed applications as well as in low-power systems, software solutions are not sufficient and a hardware implementation is therefore needed. The Parabolic Synthesis methodology is a way to implement functions in hardware based on low complexity operations that are simple to implement in hardware. A difference in the Parabolic Synthesis methodology compared to many other approximation methodologies is that it is a multiplicative, in contrast to additive, methodology. To further improve the performance of Parabolic Synthesis based designs, the methodology is combined with Second-Degree Interpolation. The paper shows that the methodology provides a significant reduction in chip area, computation delay and power consumption with preserved characteristics of the error. To evaluate this, the logarithmic function was implemented, as an example, using the Parabolic Synthesis methodology in comparison to the Parabolic Synthesis methodology combined with Second-Degree Interpolation. To further demonstrate the feasibility of both methodologies, they have been compared with the CORDIC methodology. The comparison is made on the implementation of the fractional part of the logarithmic function with a 15-bit resolution. The designs implemented using the Parabolic Synthesis methodology – with and without the Second-Degree Interpolation – perform 4x and 8x better, respectively, than the CORDIC implementation in terms of throughput. In terms of energy consumption, the CORDIC implementation consumes 140% and 800% more energy, respectively. The chip area is also smaller in the case when the Parabolic Synthesis methodology combined with Second-Degree Interpolation is used. © 2016 Elsevier B.V. All rights reserved.

  • 157.
    Hertz, Erik
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Thuning, Niclas
    Lund University, Lund, Sweden.
    Bärring, Leo
    Lund University, Lund, Sweden.
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Nilsson, Peter
    Lund University, Lund, Sweden.
    Algorithms for implementing roots, inverse and inverse roots in hardware2016Manuscript (preprint) (Other academic)
    Abstract [en]

    In applications as in future MIMO communication systems a massive computation of complex matrix operations, such as QR decomposition, is performed. In these matrix operations, the functions roots, inverse and inverse roots are computed in large quantities. Therefore, to obtain high enough performance in such applications, efficient algorithms are highly important. Since these algorithms need to be realized in hardware it must also be ensured that they meet high requirements in terms of small chip area, low computation time and low power consumption. Power consumption is particularly important since many applications are battery powered.For most unary functions, directly applying an approximation methodology in a straightforward way will not lead to an efficient implementation. Instead, a dedicated algorithm often has to be developed. The functions roots, inverse and inverse roots are in this category. The developed approaches are founded on working in a floating-point format. For the roots functions also a change of number base is used. These procedures not only enable simpler solutions but also increased accuracy, since the approximation algorithm is performed on a mantissa of limited range.As a summarizing example the inverse square root is chosen. For comparison, the inverse square root is implemented using two methodologies: Harmonized Parabolic Synthesis and Newton-Raphson method. The novel methodology, Harmonized Parabolic Synthesis (HPS), is chosen since it has been demonstrated to provide very efficient approximations. The Newton-Raphson (NR) method is chosen since it is known for providing a very efficient implementation of the inverse square root. It is also commonly used in signal processing applications for computing approximations on fixed-point numbers of a limited range. Four implementations are made; HPS with 32 and 512 interpolation intervals and NR with 1 and 2 iterations. Summarizing the comparisons of the hardware performance, the implementations HPS 32, HPS 512 and NR 1 are comparable when it comes to hardware performance, while NR 2 is much worse. However, HPS 32 stands out in terms of better performance when it comes to the distribution of the error.

  • 158.
    Hierons, Robert M.
    et al.
    Department of Computer Science, Brunel University London, Uxbridge, United Kingdom.
    Mousavi, Mohammad Reza
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Thomsen, Michael Kirkedal
    Department of Computer Science, University of Copenhagen, Copenhagen, Denmark.
    Turker, Uraz Cengiz
    Computer Engineering, Faculty of Engineering, Gebze Technical University, Kocaeli, Turkey.
    Hardness of deriving invertible sequences from finite state machines2017In: SOFSEM 2017: SOFSEM 2017: Theory and Practice of Computer Science: 43rd International Conference on Current Trends in Theory and Practice of Computer Science Limerick, Ireland, January 16–20, 2017, Proceedings / [ed] Bernhard Steffen, Christel Baier, Mark van den Brand, Johann Eder, Mike Hinchey & Tiziana Margaria, Heidelberg: Springer Berlin/Heidelberg, 2017, p. 147-160Conference paper (Refereed)
    Abstract [en]

    Many test generation algorithms use unique input/output sequences (UIOs) that identify states of the finite state machine specification M. However, it is known that UIO checking the existence of UIO sequences is PSPACE-complete. As a result, some UIO generation algorithms utilise what are called invertible sequences; these allow one to construct additional UIOs once a UIO has been found. We consider three optimisation problems associated with invertible sequences: deciding whether there is a (proper) invertible sequence of length at least K; deciding whether there is a set of invertible sequences for state set S′ that contains at most K input sequences; and deciding whether there is a single input sequence that defines invertible sequences that take state set S″ to state set S′. We prove that the first two problems are NP-complete and the third is PSPACE-complete. These results imply that we should investigate heuristics for these problems. © Springer International Publishing AG 2017.

  • 159.
    Hilt, Benoit
    et al.
    University of Haute Alsace, Colmar, France.
    Berbineau, MarionIFSTTAR, Villeneuve d’Ascq, France .Vinel, AlexeyHalmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).Pirovano, AlainENAC, Toulouse, France .
    Networking Simulation for Intelligent Transportation Systems: High Mobile Wireless Nodes2017Collection (editor) (Refereed)
    Abstract [en]

    This book studies the simulation of wireless networking in the domain of Intelligent Transportation Systems (ITS) involving aircraft, railway and vehicular communication. On this subject, particular focus is placed on effective communication channels, mobility modeling, multi-technology simulation and global ITS simulation frameworks.

    Networking Simulation for Intelligent Transportation Systems addresses the mixing of IEEE802.11p and LTE into a dedicated simulation environment as well as the links between ITS and IoT; aeronautical mobility and VHD Data Link (VDL) simulation; virtual co-simulation for railway communication and control-command; realistic channel simulation, mobility modeling and autonomic simulation for VANET and quality metrics for VANET.

    The authors intend for this book to be as useful as possible to the reader as they provide examples of methods and tools for running realistic and reliable simulations in the domain of communications for ITS.

  • 160.
    Hilt, Benoît
    et al.
    University of Haute Alsace, Mulhouse, Colmar, France.
    Berbineau, MarionFrench Institute of Science and Technology, Spatial Planning, Development, and Networks, Villeneuve d'Ascq, France.Vinel, AlexeyHalmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).Jonsson, MagnusHalmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).Pirovano, AlainÉcole Nationale de l’Aviation Civile, Toulouse, France.
    Communication Technologies for Vehicles: 14th International Workshop, Nets4Cars/Nets4Trains/Nets4Aircraft 2019, Colmar, France, May 16–17, 2019, Proceedings2019Conference proceedings (editor) (Refereed)
  • 161.
    Hoang, Hoai
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Buttazzo, Giorgio
    Real-Time Systems Laboratory Scuola Superiore Sant’Anna Pisa, Italy.
    Reducing Delay and Jitter in Software Control Systems2007In: Proceedings of the 15th International Conference on Real-Time and Network Systems: RTNS’07, Vandoeuvre: Institut National Polytechnique de Lorraine , 2007, p. 173-182Conference paper (Refereed)
    Abstract [en]

    Software control systems may be subject to high interference caused by concurrency and resource sharing. Reducing delay and jitter in such systems is crucial for guaranteeing high performance and predictability. In this paper, we present a general approach for reducing delay and jitter by acting on task relative deadlines. The method allows the user to specify a deadline reduction factor for each task to better exploit the available slack according to specific jitter sensitivity. Experimental results confirm the effectiveness and the generality of the proposed approach with respect to other methods available in the literature.

  • 162.
    Hoang, Hoai
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Buttazzo, Giorgio
    Real-Time Systems Laboratory Scuola Superiore Sant’Anna Pisa, Italy.
    Jonsson, Magnus
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Reducing delay and jitter in software control systems2007Conference paper (Refereed)
    Abstract [en]

    Software control systems may be subject to high interference caused by concurrency and resource sharing. Reducing delay and jitter in such systems is crucial for guaranteeing high performance and predictability. In this paper, we present a general approach for reducing delay and jitter by acting on task relative deadlines. The method allows the user to specify a deadline reduction factor for each task to better exploit the available slack according to specific jitter sensitivity. Experimental results confirm the effectiveness and the generality of the proposed approach with respect to other methods available in the literature.

  • 163.
    Hoang, Le-Nam
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Relaying for Timely and Reliable Applications in Wireless Networks2017Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Many emerging applications based on wireless networks involve distributed control. This implies high requirements on reliability, but also on predictable maximum delay. Further, for applications, it is vital to use off-the-shelf components, both due to cost constraints and requirements on interoperability with existing networks. This, in turn, implies that concurrent transmissions and multiuser detection are seldom possible. Instead, half-duplex time-division multiple access (TDMA) is typically used. Aiming to reduce the packet error rate given a deadline (a set of TDMA time-slots), this thesis proposes a relaying scheme, which can be implemented on top of off-the-shelf components. The relaying scheme selects the best sequence of relayers, given the number of time-slots allowed by the deadline, such that the resulting error probability is minimized at the targeted receiver(s). The scheme differs from existing work in that it considers both unicast as well as broadcast and assumes that all nodes can overhear each other, as opposed to separating source nodes, relay nodes and destination nodes into three disjoint sets. A full analysis of the resulting error probability is provided and complementary numerical results show that the proposed relay sequencing strategy significantly improves reliability given a certain maximum delay, or alternatively, reduces the delay, given a certain target reliability requirement. To illustrate the performance improvements of relay sequencing, it is incorporated in a platooning application. If the decision regarding which relayer to assign in each time-slot can be taken online, just before the transmission, much can be gained. To this end, a low-complexity algorithm is developed, which is shown to be highly likely to find the optimal combination of relaying nodes that minimizes the resulting error probability at the targeted receiver(s). Data packets in wireless automation networks is typically small. To enable timely and reliable all-to-all broadcast in such systems, relay sequencing using packet aggregation is proposed. The strategy assigns relayers to time slots, as well as determines which packets to aggregate in each slot, using the proposed low-complexity algorithm. To further increase the reliability, a clustering scheme is proposed. When a relayer in the sequence fails to overhear a correct copy, a backup relayer in the cluster takes over. This work thereby enables ultra-reliable communications with maintained end-toend delay using low-complexity techniques and off-the-shelf components.

  • 164.
    Hoang, Le-Nam
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Relaying for Timely and Reliable Message Dissemination in Wireless Distributed Control Systems2015Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Distributed control applications enabled by wireless networks are becoming more and more frequent. The advantages of wireless access are many, as control systems become mobile, autonomous and connected. Examples include platooning and automated factories. However, distributed control systems have stringent requirement on both reliability and timeliness, the latter in terms of deadlines. If the deadline is missed, the packet is considered useless, similarly to a lost or erroneous packet in a system without deadlines. In addition, wireless channels are, by nature, more exposed to noise and interference than their wired counterparts. Consequently, it implies a considerable challenge to fulfill the deadline requirements with sufficient reliability for proper functionality of distributed control applications. However, by taking advantage of cooperative communications, increased reliability can be achieved with little or no additional delay.

    Reducing the delay until a message is successfully received is a two-fold problem: providing channel access with a predictable maximum delay and maximizing the reliability of each transmission, once granted by the medium access method. To this end, this thesis proposes a framework that provides a bounded channel access delay and handles the co-existence of both time-triggered and event-driven messages encountered in distributed control applications. In addition, the thesis proposes and evaluates an efficient message dissemination technique based on relaying that maximizes the reliability given a certain deadline, or alternatively determines the delay required to achieve a certain reliability threshold for both unicast and broadcast scenarios. Numerical results, which are verified by Monte-Carlo simulations, show significant improvements with the proposed relaying scheme as compared to a conventional scheme without cooperation, providing more reliable message delivery given a fixed number of available time-slots. It also becomes clear in which situations relaying is preferable and in which situations pure retransmissions are preferable, as the relay selection algorithm will always pick the best option. The relay selection algorithm has a reasonable complexity and can be used by both routing algorithms and relaying scenarios in any time-critical application as long as it is used together with a framework that enables predictable channel access. In addition, it can be implemented on top of commercially available transceivers.

  • 165.
    Hoang, Le-Nam
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Mälardalen University, Västerås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Framework for Reliable Exchange of Periodic and Event-Driven Messages in Platoons2015In: 2015 IEEE International Conference on Communication Workshop, Piscataway: IEEE conference proceedings, 2015, p. 2471-2476Conference paper (Refereed)
    Abstract [en]

    Platooning is widely considered a promising approach to decrease fuel consumption by reducing the air drag. However, in order to achieve the benefits of aerodynamic efficiency, the inter-vehicle distances must be kept short. This implies that the intra-platoon communication must not only be reliable but also able to meet strict timing deadlines. In this paper, we propose a framework that reliably handles the co-existence of both time-triggered and event-driven control messages in platooning applications and we derive an efficient message dissemination technique. We propose a semi-centralized time division multiple access (TDMA) approach, which e.g., can be placed on top of the current standard IEEE 802.11p and we evaluate the resulting error probability and delay, when using it to broadcast periodic beacons and disseminating eventdriven messages within a platoon. Simulation results indicate that the proposed dissemination policy significantly enhances the reliability for a given number of available time-slots, or alternatively, reduces the delay, in terms of time-slots, required to achieve a certain target error probability, without degrading the performance of co-existing time-triggered messages. © 2015 IEEE

  • 166.
    Hoang, Le-Nam
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Mälardalen University, Västerås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A novel relaying scheme to guarantee timeliness and reliability in wireless networks2017In: 2016 IEEE Globecom Workshops (GC Wkshps): Proceedings, New York: IEEE, 2017, article id 7848822Conference paper (Refereed)
    Abstract [en]

    Many emerging applications based on wireless networks involve distributed control. This implies high requirements on reliability, but also on a predictable maximum delay and sometimes jitter. Further, many distributed control systems need to be constructed using off-the-shelf components, both due to cost constraints and due to interoperability with existing networks. This, in turn, implies that concurrent transmissions and multiuser detection are seldom possible. Instead, half-duplex time division multiple access (TDMA) is typically used. The total communication delay thereby depends on the packet error rate and the time until channel access is granted. With TDMA, channel access is upper-bounded and the jitter can be set to zero. With the aim to reduce the packet error rate given a certain deadline (a set of TDMA time-slots), we propose a novel relaying scheme, which can be implemented on top of off-the-shelf components. The paper includes a full analysis of the resulting error probability and latency. Numerical results show that the proposed relaying strategy significantly improves reliability given a certain maximum latency, or alternatively, reduces the latency, given a certain target reliability requirement. © 2016 IEEE.

  • 167.
    Hoang, Le-Nam
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Mälardalen University, Västerås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Simple Relaying Scheme to Guarantee Timeliness and Reliability in Wireless Networks2015Manuscript (preprint) (Other academic)
    Abstract [en]

    Many emerging applications based on wireless networks involves distributed control. This implies high requirements on reliability, but also on maximum delay and sometimes jitter. The total delay depends on the packet error rate and the time until channel access is granted. With e.g., TDMA, channel access is upper-bounded and the jitter zero. To reduce the packet error rate given a certain deadline (a set of TDMA time-slots), we propose a simple relaying scheme, including a full analysis of its resulting error probability and delay. Numerical results show that the proposed relaying strategy significantly improves reliability given a certain message deadline.

  • 168.
    Hoang, Le-Nam
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Mälardalen University, Västerås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    An Efficient Message Dissemination Technique in Platooning Applications2015In: IEEE Communications Letters, ISSN 1089-7798, E-ISSN 1558-2558, Vol. 19, no 6, p. 1017-1020Article in journal (Refereed)
    Abstract [en]

    Autonomous driving in road trains, a.k.a. platooning, may reduce fuel consumption considerably if the intervehicle distances are kept short. However, to do this, the intraplatoon communication must not only be reliable but also able to meet strict deadlines. While time-triggered messages are the foundation of most distributed control applications, platooning is likely to also require dissemination of event-driven messages. While much research work has focused on minimizing the age of periodic messages, state-of-the-art for disseminating eventdriven messages is to let all nodes repeat all messages and focus on mitigating broadcast storms. We derive an efficient message dissemination scheme based on relay selection which minimizes the probability of error at the intended receiver(s) for both unicast and broadcast, without degrading the performance of co-existing time-triggered messages. We present a full analysis of the resulting error probability and delay, when relayers, selected by our algorithm, are used to disseminate messages within a platoon. Numerical results indicate that the proposed relaying policy significantly enhances the reliability for a given delay.

  • 169.
    Hoang, Le-Nam
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Mälardalen University, Västerås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Cluster Relaying to Guarantee Timeliness and Reliability in Wireless NetworksManuscript (preprint) (Other academic)
    Abstract [en]

    Many emerging applications using wireless networks imply high requirements on reliability, but also on a predictable maximum delay. Due to cost constraints and interoperability with existing networks, half-duplex time division multiple access (TDMA) is typically used in these applications. With TDMA, channel access is upper-bounded and the jitter can be set to zero. However, the major drawback of TDMA is that the already-allocated time-slots are wasted if their respective transmitters do not have any packet to send. Therefore, in this paper we propose a novel cluster-relaying scheme to overcome this drawback but still reduce the probability of error given a certain deadline. Numerical results show that the proposed scheme significantly enhances reliability while guaranteeing deadline for each message.

  • 170.
    Hoang, Le-Nam
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Mälardalen University, Västerås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Low Complexity Algorithm for Efficient Relay Assignment in Unicast/Broadcast Wireless Networks2017In: 2017 IEEE 85th Vehicular Technology Conference (VTC Spring), [S.l.]: IEEE, 2017Conference paper (Refereed)
    Abstract [en]

    Using relayers in wireless networks enables higher throughput, increased reliability or reduced delay. However, when building networks using commercially available hardware, concurrent transmissions by multiple relayers are generally not possible. Instead one specific relayer needs to be assigned for each transmission instant. If the decision regarding which relayer to assign, i.e., which relayer that has the best opportunity to successfully deliver the packet, can be taken online, just before the transmission is to take place, much can be gained. This is particularly the case in mobile networks, as a frequently changing network topology considerably affects the choice of a suitable relayer. To this end, this paper addresses the problem of online relay assignment by developing a low-complexity algorithm highly likely to find the optimal combination of relaying nodes that minimizes the resulting error probability at the targeted receiver(s) using a mix of simulated annealing and ant colony algorithms, such that relay assignments can be made online also in large networks. The algorithm differs from existing works in that it considers both unicast as well as broadcast and assumes that all nodes can overhear each other, as opposed to separating source nodes, relay nodes and destination nodes into three disjoint sets, which is generally not the case in most wireless networks.

  • 171.
    Hoang, Le-Nam
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Mälardalen University, Västerås, Sweden.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Relaying with Packet Aggregation for Half-Duplex All-to-All Broadcast in Time-Critical Wireless Networks2017In: 2017 IEEE Globecom Workshops (GC Wkshps), Piscataway, NJ: IEEE, 2017Conference paper (Other academic)
    Abstract [en]

    Wireless automation and control networks, with stringent latency and reliability requirements, typically use half-duplex communications combined with deadline-aware scheduling of time slots to nodes. To introduce higher reliability in legacy industrial control systems, extra time slots are usually reserved for retransmissions. However, in distributed wireless control systems, where sensor data from several different nodes must be timely and reliably available at all places where controller decisions are made, this is particularly cumbersome as all nodes may not hear each other and extra time slots imply increased delay. To enable all-to-all broadcast with manageable overhead and complexity in such systems, we therefore propose a novel relaying strategy using packet aggregation. The strategy assigns relayers to time slots, as well as determines which packets to aggregate in each slot, using a low-complexity algorithm such that ultra-reliable communications can be obtained with maintained end-to-end latency.

  • 172.
    Huang, Chung-Ming
    et al.
    Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan.
    Yang Lin, Shih
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Proactive safety – cooperative collision warning for vehicles2015In: Clean Mobility and Intelligent Transport Systems / [ed] Michele Fiorini & Jia-Chin Lin, London: IET Digital Library, 2015, p. 117-134Chapter in book (Refereed)
    Abstract [en]

    Telematics is an interdisciplinary technology that combines telecommunications, vehicular technologies, road transportation, road safety, electrical engineering, and computer science to provide applications and services for the purpose of comfort and safety enhancement. From the timing point of view, the driving safety can be classified into two domains: (1) active safety and (2) passive safety. Passive safety systems are used to reduce damage and protect passengers and drivers when an accident occurs. Common passive safety systems include airbags, seatbelts, whiplash injury lessening systems, and energy absorbing steering column. Active safety systems are used to prevent accidents before they occur. An example of active safety system is the collision warning/avoidance system. It basically collects/detects neighboring vehicles' motion states to compute potential collision between vehicles. Based on future technology, cooperative active safety systems emerge. Vehicles can exchange their information between each other through wireless communication [1], for example, over a vehicular ad hoc network (VANET), for cooperative purposes such as collision warning/avoidance. In a project named smart intersection, a collision avoidance system based on the concept of active safety was developed by Ford and the US government [2]. The system collects a vehicle's information like Global Positioning System (GPS) coordinates, velocity, and heading and delivers it through wireless communication to other vehicles in order to prevent accidents and congestion before vehicles arrive to an intersection. To understand the details of cooperative collision warning (CCW), this chapter exposes main factors that affect the accuracy of CCW, challenges of CCW, communication techniques for cooperative safety, and collision prediction techniques. CCW systems are also introduced in detail. Moreover, we present some existing safety-related techniques and systems that are developed by automobile manufacturers. © The Institution of Engineering and Technology 2015

  • 173.
    Huisman, Marieke
    et al.
    University of Twente, Enschede, The Netherlands.
    Monahan, Rosemary
    Maynooth University, Maynooth, Ireland.
    Müller, Peter
    ETH Zurich, Zürich, Switzerland.
    Mostowski, Wojciech
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Ulbrich, Mattias
    Karlsruhe Institute of Technology, Karlsruhe, Germany.
    VerifyThis 2017: A Program Verification Competition2017Report (Other academic)
    Abstract [en]

    VerifyThis 2017 was a two-day program verification competition which took place from April 22-23rd, 2017 in Uppsala, Sweden as part of the European Joint Conferences on Theory and Practice of Software (ETAPS 2017). It was the sixth instalment in the VerifyThis competition series. This article provides an overview of the VerifyThis 2017 event, the challenges that were posed during the competition, and a high-level overview of the solutions to these challenges. It concludes with the results of the competition.

  • 174.
    Inoue, Jun
    et al.
    National Institute of Advanced Industrial Science and Technology, Ikeda, Osaka, Japan.
    Taha, Walid
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Reasoning about multi-stage programs2016In: Journal of functional programming (Print), ISSN 0956-7968, E-ISSN 1469-7653, Vol. 26, article id e22Article in journal (Refereed)
    Abstract [en]

    We settle three basic questions that naturally arise when verifying code generators written in multi-stage functional programming languages. First, does adding staging to a language compromise any equalities that hold in the base language? Unfortunately it does, and more care is needed to reason about terms with free variables. Second, staging annotations, as the name "annotations" suggests, are often thought to be orthogonal to the behavior of a program, but when is this formally guaranteed to be true? We give termination conditions that characterize when this guarantee holds. Finally, do multi-stage languages satisfy useful, standard extensional properties, for example, that functions agreeing on all arguments are equivalent? We provide a sound and complete notion of applicative bisimulation, which establishes such properties or, in principle, any valid program equivalence. These results yield important insights into staging and allow us to prove the correctness of quite complicated multi-stage programs. © Cambridge University Press 2016.

  • 175.
    Inoue, Jun
    et al.
    Rice University, Houston, Texas, USA.
    Taha, Walid
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Rice University, Houston, Texas, USA.
    Reasoning About Multi-Stage Programs2012In: Programming Languages and Systems: 21st European Symposium on Programming, ESOP 2012, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2012, Tallinn, Estonia, March 24 - April 1, 2012. Proceedings / [ed] Helmut Seidl, Berlin: Springer Publishing Company, 2012, Vol. 7211, p. 357-376Conference paper (Refereed)
    Abstract [en]

    We settle three basic questions that naturally arise when verifying multi-stage functional programs. Firstly, does adding staging to a language compromise any equalities that hold in the base language? Unfortunately it does, and more care is needed to reason about terms with free variables. Secondly, staging annotations, as the name “annotations” suggests, are often thought to be orthogonal to the behavior of a program, but when is this formally guaranteed to be true? We give termination conditions that characterize when this guarantee holds. Finally, do multi-stage languages satisfy useful, standard extensional facts—for example, that functions agreeing on all arguments are equivalent? We provide a sound and complete notion of applicative bisimulation, which establishes such facts or, in principle, any valid program equivalence. These results greatly improve our understanding of staging, and allow us to prove the correctness of quite complicated multi-stage programs. © 2012 Springer-Verlag.

  • 176.
    Johnsson, Dennis
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Bengtsson, Jerker
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Two-level Reconfigurable Architecture for High-Performance Signal Processing2004In: ERSA'04, The 2004 International Conference on Engineering of Reconfigurable Systems and Algorithms: The 2004 International MultiConference in Computer Science and Computer Engineering / [ed] Toomas P. Plaks, Arthens: CSREA Press, 2004, p. 177-183Conference paper (Refereed)
    Abstract [en]

    High speed signal processing is often performed as a pipeline of functions on streams or blocks of data. In order to obtain both flexibility and performance, parallel, reconfigurable array structures are suitable for such processing. The array topology can be used both on the micro and macro-levels, i.e. both when mapping a function on a fine-grained array structure and when mapping a set of functions on different nodes in a coarse-grained array. We outline an architecture on the macro-level as well as explore the use of an existing, commercial, word level reconfigurable architecture on the micro-level. We implement an FFT algorithm in order to determine how much of the available resources are needed for controlling the computations. Having no program memory and instruction sequencing available, a large fraction, 70%, of the used resources is used for controlling the computations, but this is still more efficient than having statically dedicated resources for control. Data can stream through the array at maximum I/O rate, while computing FFTs. The paper also shows how pipelining of the FFT algorithm over a two-level reconfigurable array of arrays can be done in various ways, depending on the application demands.

  • 177.
    Johnsson, Dennis
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Åhlander, Anders
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Analyzing the Advantages of Run-Time Reconfiguration in Radar Signal Processing2005In: Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems / [ed] S. Q. Zheng, Anaheim: ACTA Press, 2005, p. 701-706Conference paper (Refereed)
    Abstract [en]

    Configurable architectures have emerged as one of the most powerful programmable signal processing platforms commercially available, obtaining their performance through the use of spatial parallelism. By changing the functionality of these devices during run-time, flexible mapping of signal processing applications can be made. The run-time flexibility puts requirements on the reconfiguration time that depend both on the application and on the mapping strategy. In this paper we analyze one such application, Space Time Adaptive Processing for radar signal processing, and show three different mappings and their requirements. The allowed time for run-time reconfiguration in these three cases varies from 1 ms down to 1 µs. Each has its own advantages, such as data reuse and optimization of computational kernels. Architectures with reconfiguration times in the order of 10 µs provide the flexibility needed for mapping the example in an efficient way, allowing for on-chip data reuse between the different processing stages.

  • 178.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Control-channel based fiber-ribbon pipeline ring network1998In: Fifth International Conference on Massively Parallel Processing: proceedings : June 15-18, 1998, Las Vegas, Nevada, Piscataway, NJ.: IEEE , 1998, p. 158-165Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a control-channel based ring network built up of fiber-ribbon point-to-point links. One of the fibers in each link forms part of the control-channel ring, over which medium access control information is sent immediately before data transmissions. This increases performance of the network. High throughputs can be achieved in the network due to pipelining, i.e., several packets can be traveling through the network simultaneously but in different segments of the ring. The network can meet high performance demands in, e.g., massively parallel signal processing systems, which is shown by example in the paper. Also, real-time demands can be met using slot reserving. The network, called CC-FPR (Control-Channel based Fiber-ribbon Pipeline Ring), can be built today using fiber-optic off-the-shelf components, and a prototype is currently under development. The increasingly good price/performance ratio for fiber-ribbon links indicates a great success potential for the proposed kind of network.

  • 179.
    Jonsson, Magnus
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Optical interconnection technology in switches, routers and optical cross connects2003In: Optical Networks Magazine, ISSN 1388-6916, E-ISSN 1388-6916, Vol. 4, no 4, p. 20-34Article in journal (Refereed)
    Abstract [en]

    The performance of data- and telecommunication equipment must keep abreast of the increasing network speed. At the same time, it is necessary to deal with the internal interconnection complexity, which typically grows by N2 or NlogN, where N is the number of ports. This requires new interconnection technologies to be used internally in the equipment. Optical interconnection technology is a promising alternative and much work has already been done. This paper reviews a number of optical and optoelectronic interconnection architectures, especially from a data and telecommunication equipment point of view. Three kinds of systems for adopting optical interconnection technology are discussed: (i) optical cross connects (OXCs), (ii) switches and routers with some kind of burst switching and (iii) switches and routers that redirect traffic on the packet or cell level. The interconnection technologies and architectures are discussed according to their suitability for adoption in the three system types.

  • 180.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Optical Interconnection Technology in Switches, Routers and Optical Cross Connects2001In: International Conference on Parallel Processing Workshops, 2001, IEEE Computer Society , 2001, p. 319-326, article id 951968Conference paper (Refereed)
    Abstract [en]

    The performance of data- and telecommunication equipment must keep up with the increasing network speed. At the same time, one must deal with the internal interconnection complexity, often growing exponentially with the number of ports. Therefore, new interconnection technologies to be used internally in the equipment are needed. Optical interconnection technology is a promising alternative and much work has been done. In this paper, a number of optical and optoelectronic interconnection architectures are reviewed, especially from a data- and telecommunication equipment point-of-view. Three kinds of systems for adoption of optical interconnection technology are discussed: (i) optical cross connects (OXCs), (ii) switches and routers with some kind of burst switching, and (iii) switches and routers which redirect traffic on the packet or cell level. The reviewed interconnection technologies and architectures are discussed according to their suitability of adoption in the three mentioned system types.

  • 181.
    Jonsson, Magnus
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Why real-time communication matters2011Conference paper (Refereed)
    Abstract [en]

    Embedded systems normally need to react to external events in time if the application requirements are to be met. Moreover, as embedded systems more and more often consist of distributed sub-systems and nodes, they must rely on communication networks. Real-time communication methods and protocols are essential for such systems and must be chosen and developed carefully. Not only real-time demands must be supported, but also high throughput, low energy consumption, high reliability and cost-efficiency, depending on the specific application. Another challenge to consider comes from the dynamics in systems properties and application requirements in some applications. Novel cooperative embedded systems might even rely on wireless connectivity where mobility and the erroneous nature of the communication medium bring new challenges. In this paper, we give examples of challenges, applications and solutions to give an understanding of the importance and possibilities of real-time communication. The aim is also to give a brief overview of research on real-time communication performed at Halmstad University, and in what contexts the results can be useful. Both systems relying on wired and wireless communication are covered.

  • 182.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Börjesson, Klas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Legardt, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Dynamic time-deterministic traffic in a fiber-optic WDM star network1997In: Proceedings: Ninth Euromicro Workshop on Real Time Systems, June 11-13, 1997, Toledo, Spain, Piscataway, NJ.: IEEE Computer Society, 1997, p. 25-33, article id 613760Conference paper (Refereed)
    Abstract [en]

    A number of protocols for WDM (Wavelength Division Multiplexing) star networks have been proposed. However, the area of real-time protocols for these networks is quite unexplored. In this paper, a real-time protocol, based on TDM (Time Division Multiplexing), for fiber-optic star networks is presented. By the use of WDM, multiple Gb/s channels are achieved. Services for both guarantee-seeking messages and best-effort messages are supported for single destination, multicast, and broadcast transmission. Slot reserving can be used to increase the time-deterministic bandwidth, while still having an efficient bandwidth utilization due to a simple slot release method. The deterministic properties of the protocol are analyzed and simulation results presented. © 1997 IEEE

  • 183.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Kunert, Kristina
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    MC-EDF: A control-channel based wireless multichannel MAC protocol with real-time support2012In: Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies and Factory Automation, ETFA 2012: September 17-21, 2012, Krakow, Poland, Piscataway, US: Institute of Electrical and Electronics Engineers , 2012, article id 6489558Conference paper (Refereed)
  • 184.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Kunert, Kristina
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Bilstrup, Urban
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A real-time medium access protocol supporting dynamic spectrum allocation in industrial networks2013In: Multiple Access Communications: 6th International Workshop, MACOM 2013, Vilnius, Lithuania, December 16-17, 2013. Proceedings / [ed] Magnus Jonsson, Alexey Vinel, Boris Bellalta, Ninoslav Marina, Desislava Dimitrova, Dieter Fiems, Heidelberg: Springer, 2013, p. 54-69Conference paper (Refereed)
    Abstract [en]

    Cognitive radio with spectrum sensing and spectrum reuse has great opportunities for industrial networking. Adapting to the current interference situation and utilising the available frequencies in an effective manner can greatly improve the data delivery capabilities. At the same time, real-time demands must be met. In this paper, we present a medium access control protocol supporting dynamic spectrum allocation as done in cognitive radio networks, providing deterministic medium access for heterogeneous traffic. The possibility of spectrum sensing in the nodes opens up for the possibility of increasing successful data transmissions, and a real-time analysis framework with three formalized constraints to be tested provides support for guaranteed timely treatment of hard real-time traffic. The real-time analysis framework includes a new type of delay check that more exactly bounds the delay compared to earlier work. Simulation experiments and performance comparisons are provided. © 2013 Springer International Publishing

  • 185.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Kunert, Kristina
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Böhm, Annette
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Increased communication reliability for delay-sensitive platooning applications on top of IEEE 802.11p2013In: Communication Technologies for Vehicles: 5th International Workshop, Nets4Cars/Nets4Trains 2013, Villeneuve d’Ascq, France, May 14-15, 2013. Proceedings / [ed] Marion Berbineau, Magnus Jonsson, Jean-Marie Bonnin, Soumaya Cherkaoui, Marina Aguado, Cristina Rico-Garcia, Hassan Ghannoum, Rashid Mehmood, Alexey Vinel, Heidelberg: Springer Berlin/Heidelberg, 2013, p. 121-135Conference paper (Refereed)
    Abstract [en]

    Cooperative driving in platooning applications has received much attention lately due to its potential to lower fuel consumption and improve safety and efficiency on our roads. However, the recently adopted standard for vehicular communication, IEEE 802.11p, fails to support the level of reliability and real-time properties required by highly safety-critical applications. In this paper, we propose a communication and real-time analysis framework over a dedicated frequency channel for platoon applications and show that our retransmission scheme is able to decrease the message error rate of control data exchange within a platoon of moderate size by several orders of magnitude while still guaranteeing that all delay bounds are met. Even for long platoons with up to seventeen members the message error rate is significantly reduced by retransmitting erroneous packets without jeopardizing the timely delivery of regular data traffic. © 2013 Springer-Verlag.

  • 186.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Kunert, Kristina
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Kallerdahl, Anders
    Mentor Graphics Scandinavia AB, Gothenburg, Sweden.
    Analysing AFDX Networks Using End-to-end Response Time Analysis2015In: Journal of Interconnection Networks (JOIN), ISSN 0219-2659, Vol. 14, no 4, article id 1350017Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a novel real-time analysis framework for AFDX (Avionics Full Duplex Switched Ethernet) networks. The framework, based on end-to-end response time analysis, calculates not only delay bounds, but also the maximum jitter for each VL (Virtual Link) at each hop, which is necessary according to the AFDX standard. Moreover, the framework supports multicasting, i.e., VLs with several paths, and VLs with arbitrary delay bounds, i.e., shorter, longer, or equal to their periods. An analysis method to calculate the worst-case buffer population is included in the framework, as it is important to guarantee that no buffer-overflow occurs. With a performance surpassing that of Network Calculus and comparable with Trajectory Approach, our framework presents a good choice due to its many features and its foundation in well-accepted analysis methods.

  • 187.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Rak, Jacek
    Gdańsk University of Technology, Gdańsk, Polen.
    Dimitri, Papadimitriou
    Nokia Bell Labs, Antwerp, Belgium.
    Arun, Somani
    Iowa State University, Iowa, United States.
    RNDM 2016 Workshop and 2nd Meeting of COST CA15127-RECODIS: Highlights from the Resilience Week in Halmstad, Sweden2017In: IEEE Communications Magazine, ISSN 0163-6804, E-ISSN 1558-1896, Vol. 55, no 5, p. 21-21Article in journal (Other (popular science, discussion, etc.))
  • 188.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Rak, JacekGdańsk University of Technology, Gdańsk, Poland.Somani, ArunIowa State University, Ames, USA.Papadimitriou, DimitriNokia Bell Labs, Antwerp, Belgium.Vinel, AlexeyHalmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Proceedings of 2016 8th International Workshop on Resilient Networks Design and Modeling (RNDM) 2016Conference proceedings (editor) (Refereed)
  • 189.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Vinel, AlexeyHalmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).Bellalta, BorisPompeu Fabra University, Barcelona, Spain.Belyaev, EvgenyTampere University of Technology, Tampere, Finland.
    Multiple Access Communications: 7th International Workshop, MACOM 20142014Conference proceedings (editor) (Refereed)
  • 190.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Vinel, AlexeyTempere University of Technology, Finland.Bellalta, BorisUniversitat Pompeu Fabra, Barcelona, Spain.Marina, NinoslavThe University of Information Science and Technology “St. Paul the Apostle”, Ohrid, Republic of Macedonia.Dimitrova, DesislavaUniversity of Bern, Switzerland.Fiems, DieterGhent University, Belgium.
    Multiple Access Communications: 6th International Workshop, MACOM 2013, Vilnius, Lithuania, December 16-17, 2013, Proceedings2013Conference proceedings (editor) (Refereed)
  • 191.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Vinel, AlexeyHalmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).Bellalta, BorisUniversitat Pompeu Fabra, Barcelona, Catalonia, Spain.Tirkkonen, OlavAalto University, Espoo, Finland.
    Multiple Access Communications: 8th International Workshop, MACOM 2015, Helsinki, Finland, September 3-4, 2015, Proceedings2015Conference proceedings (editor) (Refereed)
  • 192.
    Jonsson, Magnus
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Wiberg, Per-Arne
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Wickström, Nicholas
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), CAISR - Center for Applied Intelligent Systems Research.
    Vision-based low-level navigation using a feed-forward neural network1997In: Proc. International Workshop on Mechatronical Computer Systems for Perception and Action (MCPA'97), Pisa, Italy, Feb. 10-12, 1997, p. 105-111Conference paper (Refereed)
    Abstract [en]

    In this paper we propose a simple method for low-level navigation for autonomous mobile robots, employing an artificial neural network. Both corridor following and obstacle avoidance in indoor environments are managed by the same network. Raw grayscale images of size 32 x 23 pixels are processed one at a time by a feed-forward neural network. The output signals from the network directly control the motor control system of the robot. The feed-forward network is trained using the RPROP algorithm. Experiments in both familiar and unfamiliar environments are reported.

  • 193.
    Kang, Jiawen
    et al.
    Guangdong University of Technology, Guangzhou, China & Guangdong Key Laboratory of IoT Information Technology, Guangzhou, China.
    Yu, Rong
    Guangdong University of Technology, Guangzhou, China & Guangdong Key Laboratory of IoT Information Technology, Guangzhou, China.
    Huang, Xumin
    Guangdong University of Technology, Guangzhou, China & Guangdong Key Laboratory of IoT Information Technology, Guangzhou, China.
    Jonsson, Magnus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Bogucka, Hanna
    Poznan University of Technology, Poznan, Poland.
    Gjessing, Stein
    Zhang, Yan
    University of Oslo, Oslo, Norway & Simula Research Laboratory, Fornebu, Norway.
    Location privacy attacks and defenses in cloud-enabled internet of vehicles2016In: IEEE wireless communications, ISSN 1536-1284, E-ISSN 1558-0687, Vol. 23, no 5, p. 52-59Article in journal (Refereed)
    Abstract [en]

    As one of the promising branches of the Internet of Things, the cloud-enabled Internet of Vehicles (CE-IoV) is envisioned to serve as an essential data sensing, exchanging, and processing platform with powerful computing and storage capabilities for future intelligent transportation systems. The CE-IoV shows great promise for various emerging applications. In order to ensure uninterrupted and high-quality services, a vehicle should move with its own VM via live VM migration to obtain real-time location-based services. However, the live VM migration may lead to unprecedented location privacy challenges. In this article, we study location privacy issues and defenses in CE-IoV. We first present two kinds of unexplored VM mapping attacks, and thus design a VM identifier replacement scheme and a pseudonym-changing synchronization scheme to protect location privacy. We carry out simulations to evaluate the performance of the proposed schemes. Numerical results show that the proposed schemes are effective and efficient with high quality of privacy. © 2016 IEEE.

  • 194.
    Karlsson, Kristian
    et al.
    SP Technical Research Institute of Sweden, Borås, Sweden.
    Carlsson, Jan
    SP Technical Research Institute of Sweden, Borås, Sweden.
    Larsson, Marcus
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES). Qamcom Research and Technology AB, Gothenburg, Sweden.
    Bergenhem, Carl
    Qamcom Research and Technology AB, Gothenburg, Sweden.
    Evaluation of the V2V channel and diversity potential for platooning trucks2016In: 2016 10th European Conference on Antennas and Propagation (EuCAP), Piscataway: IEEE conference proceedings, 2016Conference paper (Refereed)
    Abstract [en]

    This paper gives results from Vehicle-to-Vehicle (V2V) communication field tests in a platoon consisting of four trucks. During these tests it was assumed that large vehicles such as trucks need multiple antennas to overcome shadowing and obstruction caused by the vehicle itself, trailers and other trucks in the platoon. Therefore, in the experiments the vehicles had one antenna in each side-view mirror, and each antenna was connected to an IEEE 802.11p radio transmitting at 5.9 GHz according to the ETSI ITS-G5 standard. The purpose of the tests was to estimate the V2V channel for trucks participating in a platoon and to investigate the potential of diversity for such cooperative application. Three communication schemes for diversity were evaluated: receive diversity, transmit diversity, and transmit in combination with receive diversity. Studies were performed for two different antenna configurations in three different environments (rural, highway and tunnel). © 2016 IEEE

  • 195.
    Kassab, Mohamed
    et al.
    HANA Laboratory, Manouba, Tunisia.
    Berbineau, MarionIFSTTAR, Villeneuve d’Ascq, France.Vinel, AlexeyHalmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).Jonsson, MagnusHalmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).Garcia, FabienENAC, Toulouse, France.Soler, JoséTechnical University of Denmark, Kgs. Lyngby, Denmark.
    Communication Technologies for Vehicles: 8th International Workshop, Nets4Cars/Nets4Trains/Nets4Aircraft 2015, Sousse, Tunisia, May 6-8, 2015. Proceedings2015Conference proceedings (editor) (Refereed)
  • 196.
    Kaur, Kuljeet
    et al.
    Thapar University, Patiala, Punjab, India.
    Dua, Amit
    Thapar University, Patiala, Punjab, India.
    Jindal, Anish
    Thapar University, Patiala, Punjab, India.
    Kumar, Neeraj
    Thapar University, Patiala, Punjab, India.
    Singh, Mukesh
    Thapar University, Patiala, Punjab, India.
    Vinel, Alexey
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    A Novel Resource Reservation Scheme for Mobile PHEVs in V2G Environment using Game Theoretical Approach2015In: IEEE Transactions on Vehicular Technology, ISSN 0018-9545, E-ISSN 1939-9359, Vol. 64, no 12, p. 5653-5666Article in journal (Refereed)
    Abstract [en]

    With the widespread penetration of plug-in hybrid electric vehicles (PHEVs), the overall demand on micro-grids (MGs) may increase manifold in the near future. Unregulated power demands from PHEVs may increase the demand-supply gap at MG. Thus, in order to keep MGs stabilize, and cater the ever growing energy demands, there is a requirement of an intelligent solution to regulate, and manage PHEVs in vehicle-togrid (V2G) environment. Keeping in view the above issues, this paper proposes a novel scheme which aims to regulate PHEVs? charging, and discharging activities based on MGs? day-ahead load curves. These load curves are obtained by utilizing the existing load forecasting techniques such as-fuzzy logic (FL), and artificial neural networks (ANN). Efficient utilization of PHEVs according to these curves may play a vital role in flattening MG?s load profile. Thus, the proposed scheme works by reserving resources such as-time slots, and charging points for PHEVs during peak shaving, and valley filling. Different algorithms pertaining to resource reservation for PHEVs have also been designed. These algorithms employ the concepts of game theory, and 0/1 knapsack problem for supporting peak shaving, and valley filling respectively. Moreover, PHEVs are also utilized when there are transitions from valley filling to peak shaving areas in the load curves, and vice-versa. PHEVs involved in this process have both charging, and discharging capabilities, and are referred as dual-mode PHEVs. The proposed scheme has been tested with respect to various parameters, and its performance was found satisfactory. © 2015 IEEE

  • 197.
    Keshishzadeh, Sarmen
    et al.
    Eindhoven University of Technology, Eindhoven, The Netherlands.
    Mooij, Arjan
    Embedded Systems Innovation by TNO, Eindhoven, The Netherlands.
    Mousavi, Mohammad Reza
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Early Fault Detection in DSLs using SMT Solving and Automated Debugging2013In: Software Engineering and Formal Methods: 11th International Conference, SEFM 2013, Madrid, Spain, September 2013 Proceedings / [ed] Robert Hierons, Mercedes G. Merayo & Mario Bravetti, Berlin: Springer Berlin/Heidelberg, 2013, Vol. 8137, p. 182-196Conference paper (Refereed)
    Abstract [en]

    In the context of Domain Specic Languages (DSLs), westudy ways to detect faults early in the software development cycle. Wepropose techniques that validate a wide range of properties, classiedinto basic and advanced. Basic validation includes syntax checking, reference checking and type checking. Advanced validation concerns domainspecic properties related to the semantics of the DSL. For verication,we mechanically translate the DSL instance and the advanced propertiesinto Satisability Modulo Theory (SMT) problems, and solve these problems using an SMT solver. For user feedback, we extend the vericationwith automated debugging, which pinpoints the causes of the violatedproperties and traces them back to the syntactic constructs of the DSL.We illustrate this integration of techniques using an industrial case oncollision prevention for medical imaging equipment. © 2013 Springer-Verlag.

  • 198.
    Khakpour, Narges
    et al.
    Linnaeus University, Växjö, Sweden.
    Mousavi, Mohammad Reza
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Notions of Conformance Testing for Cyber-Physical Systems: Overview and Roadmap2015In: 26th International Conference on Concurrency Theory: CONCUR’15, September 1–4, 2015, Madrid, Spain / [ed] Luca Aceto & David de Frutos Escrig, Wadern: Dagstuhl Publishing , 2015, Vol. 42, p. 18-40Conference paper (Other (popular science, discussion, etc.))
    Abstract [en]

    We review and compare three notions of conformance testing for cyber-physical systems. We begin with a review of their underlying semantic models and present conformance-preserving translations between them. We identify the differences in the underlying semantic models and the various design decisions that lead to these substantially different notions of conformance testing. Learning from this exercise, we reflect upon the challenges in designing an “ideal” notion of conformance for cyber-physical systems and sketch a roadmap of future research in this domain.

  • 199.
    Khamespanah, Ehsan
    et al.
    University of Tehran, School of Electrical and Computer Engineering, Tehran, Iran & Reykjavik University, School of Computer Science, Reykjavik, Island.
    Sirjani, Marjan
    Reykjavik University, School of Computer Science, Reykjavik, Island.
    Mousavi, Mohammad Reza
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Sabahi Kaviani, Zeynab
    University of Tehran, School of Electrical and Computer Engineering, Tehran, Iran.
    Razzazi, Mohammad Reza
    Amirkabir University of Technology, School of Computer Eng. and Information Tech., Tehran, Iran.
    State Distribution Policy for Distributed Model Checking of Actor Models2015In: Electronic Communications of the EASST, ISSN 1863-2122, E-ISSN 1863-2122, Vol. 72, p. 1-15Article in journal (Refereed)
    Abstract [en]

    Model checking temporal properties is often reduced to finding accepting cycles in Buchi automata. A key ingredient for an effective distributed model ¨ checking technique is a distribution policy that does not split the potential accepting cycles of the corresponding automaton among several nodes. In this paper, we introduce a distribution policy to reduce the number of split cycles. This policy is based on the call dependency graph, obtained from the message passing skeleton of the model. We prove theoretical results about the correspondence between the cycles of call dependency graph and the cycles of the concrete state space and provide empirical data obtained from applying our distribution policy in state space generation and reachability analysis. We take Rebeca, an imperative interpretation of actors, as our modeling language and implement the introduced policy in its distributed state space generator. Our technique can be applied to other message-driven actor-based models where concurrent objects or services are units of concurrency.

  • 200.
    Khan, Zeshan Aslam
    et al.
    Halmstad University, School of Information Technology. International Islamic University, Islamabad, Pakistan.
    Pignaton de Freitas, Edison
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Larsson, Tony
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Abbas, Haider
    King Saud University, Riyadh, Saudi Arabia.
    A Multi-agent Model for Fire Detection in Coal Mines using Wireless Sensor Networks2013In: 2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications / [ed] Lisa O’Conner, Los Alamitos, CA: IEEE Computer Society, 2013, p. 1754-1761, article id 6681047Conference paper (Refereed)
    Abstract [en]

    This paper presents an application for monitoring and detection of fire in coal mines using wireless sensor networks (WSNs). The application uses BDI (Belief, Desire and Intention) based multi-agent model and its implementation on sensor networks. The language used for implementation is interpreted by Jason; an extension of AgentSpeak which is based on the BDI Architecture. The BDI agents are reactive planning systems; systems that are not meant to compute the value of a function and terminate but rather designed to be permanently running and reacting to some form of event. The distributed model of the environment is adopted to overcome the communication overhead, power consumption, network delay and reliability on a centralized base station. © 2013 IEEE.

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