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  • 101.
    Noroozi, Neda
    et al.
    Eindhoven University of Technology, Eindhoven, The Netherlands.
    Mousavi, Mohammad Reza
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Willemse, Tim A.C.
    Eindhoven University of Technology, Eindhoven, The Netherlands.
    On the Complexity of Input Output Conformance Testing2014Inngår i: Formal Aspects of Component Software: 10th International Symposium, FACS 2013, Nanchang, China, October 27-29, 2013, Revised Selected Papers / [ed] José Luiz Fiadeiro, Zhiming Liu & Jinyun Xue, Heidelberg: Springer, 2014, s. 291-309Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Input-output conformance (ioco) testing is a well-known approach to model-based testing. In this paper, we study the complexity of checking ioco. We show that the problem of checking ioco is PSPACE-complete. To provide a more efficient algorithm, we propose a more restricted setting for checking ioco, namely with deterministic models and show that in this restricted setting ioco checking can be performed in polynomial time. © 2014 Springer International Publishing Switzerland.

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  • 102.
    Oliveira, Bruno
    et al.
    Universidade Federal de Pernambuco, Centro de Informática, Brazil.
    Carvalho, Gustavo
    Universidade Federal de Pernambuco, Centro de Informática, Brazil.
    Mousavi, Mohammad Reza
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Sampaio, Augusto
    Universidade Federal de Pernambuco, Centro de Informática, Brazil.
    Simulation of hybrid systems from natural-language requirements2018Inngår i: 2017 13th IEEE Conference on Automation Science and Engineering (CASE), Piscataway, NJ: IEEE Computer Society, 2018, s. 1320-1325Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Cyber-physical systems are characterised by a massive and tight interaction between computer systems and physical components. Hybrid systems provide an abstraction for modelling cyber-physical systems by featuring the integration of discrete and continuous behavioural aspects. Simulation is an important tool for validating hybrid system models, which are often too complex to be treated using other validation and verification techniques. Motivated by the industrial need for such tools, we propose a strategy (h-NAT2TEST) for simulation of hybrid systems from natural-language requirements. Using the proposed approach, one writes the system specification using a controlled natural language, from which an informal semantics is automatically inferred based on the case grammar theory. Then, a formal representation is built considering a model of hybrid data-flow reactive systems (h-DFRS). Finally, in order to allow for rigorous simulation, an Acumen specification is derived from the h-DFRS model. Simulation is supported by the Acumen modelling environment. A DC-DC boost converter is used as a case study to illustrate the overall approach. © 2017 IEEE.

  • 103.
    Osaiweran, Ammar A. H.
    et al.
    Eindhoven University of Technology, Eindhoven, The Netherlands.
    Boosten, Marcel
    Philips Healthcare, CardioVascular X-Ray, Best, The Netherlands.
    Mousavi, Mohammad Reza
    Eindhoven University of Technology, Eindhoven, The Netherlands.
    Analytical software design: introduction and industrial experience report2010Rapport (Annet vitenskapelig)
  • 104.
    Raffelsieper, M.
    et al.
    CS Dept., TU/Eindhoven, Eindhoven, Netherlands.
    Mousavi, Mohammad Reza
    CS Dept., TU/Eindhoven, Eindhoven, Netherlands.
    Strolenberg, C.
    Fenix, Eindhoven, Netherlands.
    Checking and deriving module paths in Verilog cell library descriptions2010Inngår i: Design, Automation and Test in Europe Conference & Exhibition 2010 (DATE’10, Dresden, Germany, March 8-12, 2010), Los Alamitos, Calif.: IEEE Computer Society, 2010, s. 1506-1511Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Module paths are often used to specify the delays of cells in a Verilog cell library description, which define the propagation delay for an event from an input to an output. Specifying such paths manually is an error prone task; a forgotten path is interpreted as a zero delay, which can cause further flaws in the subsequent design steps. Moreover, one can specify superfluous module paths, i.e., module paths that can never occur in any practical run of the model and hence, make excessive restrictions on the subsequent design decision. This paper presents a method to check whether the given module paths are reflected in the functional implementation. Complementing this check, we also present a method to derive module paths from a functional description of a cell. © 2010 EDAA.

  • 105.
    Raffelsieper, M.
    et al.
    Department of Computer Science, TU Eindhoven, P.O. Box 513, 5600 MB Eindhoven, Netherlands.
    Mousavi, Mohammad Reza
    Institute for Computing and Information Sciences, Radboud University Nijmegen, P.O. Box 9010, 6500 GL Nijmegen, Netherlands.
    Zantema, H.
    Institute for Computing and Information Sciences, Radboud University Nijmegen, P.O. Box 9010, 6500 GL Nijmegen, Netherlands.
    Order-independence of vector-based transition systems2010Inngår i: Proceedings 10th International Conference on Application of Concurrency to System Design (ACSD’10, Braga, Portugal, June 21-25, 2010), Los Alamitos, Calif.: IEEE Computer Society, 2010, s. 115-123Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Semantics of many specification languages, particularly those used in the domain of hardware, is described in terms of vector-based transition systems. In such a transition system, each macro-step transition is labeled by a vector of inputs. When performing a macro-step, several inputs may potentially change. Each macro-step can thus be decomposed in a number of micro-steps, taking one input change at a time into account. This is akin to an interleaving semantics, where a concurrent step is represented by an interleaving of its constituting components. We present abstract criteria on vector-based transition systems, which guarantee that the next state computation is independent of the order in which these micro-steps are executed. If our abstract criteria are satisfied by the semantic definition of a certain specification, then its state-space generation or exploration algorithm needs to only consider one representative among all possible permutations of such micro-steps. We demonstrate the applicability of our abstract criteria to the specification of transistor netlists. © 2010 IEEE.

  • 106.
    Raffelsieper, Matthias
    et al.
    Department of Computer Science, TU/Eindhoven, P.O. Box 513, 5600 MB, Eindhoven, The Netherlands.
    Mousavi, Mohammad Reza
    Department of Computer Science, TU/Eindhoven, P.O. Box 513, 5600 MB, Eindhoven, The Netherlands.
    Symbolic Power Analysis of Cell Libraries2011Inngår i: Formal Methods for Industrial Critical Systems: Proceedings / [ed] Salaun, G, Schatz, B, Berlin: Springer Berlin/Heidelberg, 2011, Vol. 6959, s. 134-148Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Cell libraries are collections of logic cores (cells) used to construct larger chip designs; hence, any reduction in their power consumption may have a major impact in the power consumption of larger designs. The power consumption of a cell is often determined by triggering it with all possible input values in all possible orders at each state. In this paper, we first present a technique to measure the power consumption of a cell more efficiently by reducing the number of input orders that have to be checked. This is based on symbolic techniques and analyzes the number of (weighted) wire chargings taking place. Additionally, we present a technique that computes for a cell all orders that lead to the same state, but differ in their power consumption. Such an analysis is used to select the orders that minimize the required power, without affecting functionality, by inserting sufficient delays. Both techniques have been evaluated on an industrial cell library and were able to efficiently reduce the number of orders needed for power characterization and to efficiently compute orders that consume less power for a given state and input-vector transition.

  • 107.
    Raffelsieper, Matthias
    et al.
    Department of Computer Science, TU Eindhoven, P.O. Box 513, Eindhoven, The Netherlands.
    Mousavi, Mohammad Reza
    Department of Computer Science, TU Eindhoven, P.O. Box 513, Eindhoven, The Netherlands.
    Roorda, Jan-Willem
    Fenix Design Automation, P.O. Box 920, Eindhoven, The Netherlands.
    Strolenberg, Chris
    Fenix Design Automation, P.O. Box 920, Eindhoven, The Netherlands.
    Zantema, Hans
    Department of Computer Science, TU Eindhoven, P.O. Box 513, Eindhoven, The Netherlands.
    Formal analysis of non-determinism in Verilog cell library simulation models2009Inngår i: Formal Methods for Industrial Critical Systems: 14th International Workshop, FMICS 2009, Eindhoven, The Netherlands, November 2-3, 2009. Proceedings / [ed] María Alpuente, Byron Cook, Christophe Joubert, Berlin: Springer Berlin/Heidelberg, 2009, Vol. 5825, s. 133-148Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Cell libraries often contain a simulation model in a system design language, such as Verilog. These languages usually involve non-determinism, which in turn, poses a challenge to their validation. Simulators often resolve such problems by using certain rules to make the specification deterministic. This however is not justified by the behavior of the hardware that is to be modeled. Hence, simulation might not be able to detect certain errors. In this paper we develop a technique to prove whether non-determinism does not affect the behavior of the simulation model, or whether there exists a situation in which the simulation model might produce different results. To make our technique efficient, we show that the global property of equal behavior for all possible evaluations is equivalent to checking only a certain local property.

  • 108.
    Raffelsieper, Matthias
    et al.
    TU Eindhoven, Dept Comp Sci, NL-5600 MB Eindhoven, Netherlands.
    Mousavi, Mohammad Reza
    TU Eindhoven, Dept Comp Sci, NL-5600 MB Eindhoven, Netherlands.
    Zantema, Hans
    TU Eindhoven, Dept Comp Sci, NL-5600 MB Eindhoven, Netherlands.
    Long-run order-independence of vector-based transition systems2011Inngår i: IET Computers & Digital Techniques, ISSN 1751-8601, E-ISSN 1751-861X, Vol. 5, s. 468-478Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Semantics of many specification languages, particularly those used in the domain of hardware, is described in terms of vector-based transition systems. In such transition systems, each macro-step transition is labeled by a vector of inputs in which several inputs may change simultaneously. Each macro-step can thus be decomposed into a number of micro-steps, considering one input change at a time. This is akin to an interleaving semantics, where a concurrent step is represented by an interleaving of its constituting components. In this paper, the authors present abstract criteria on vector-based transition systems, which guarantee the next state computation to be independent of the execution order of micro-steps. If these abstract criteria are satisfied, then state-space generation or exploration algorithms only need to consider one representative among all possible permutations of micro-steps. For most practical applications only the system's long-run behaviour is of relevance and the transient start-up phase can be ignored. Hence, the authors customise their generic techniques to focus on the long-run behaviour and identify orders of interleaving input changes that may behave differently during start-up, but compute the same next states in the long-run behaviour. Applicability of the developed abstract criteria is demonstrated for specifications of transistor netlists. ©2011, IEEE.

  • 109.
    Raffelsieper, Matthias
    et al.
    Department of Computer Science TU Eindhoven, P.O. Box 513 Eindhoven, The Netherlands.
    Roorda, Jan-Willem
    Fenix Design Automation P.O. Box 920 Eindhoven, The Netherlands.
    Mousavi, Mohammad Reza
    Department of Computer Science TU Eindhoven, P.O. Box 513 Eindhoven, The Netherlands.
    Model checking Verilog descriptions of cell libraries2009Inngår i: 2009 Ninth International Conference on Application of Concurrency to System Design: Proceedings, Los Alamitos, Calif.: IEEE Computer Society, 2009, s. 128-137Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We present a formal semantics for a subset of Verilog, commonly used to describe cell libraries, in terms of transition systems. Such transition systems can serve as input to symbolic model checking, for example equivalence checking with a transistor netlist description. We implement our formal semantics as an encoding from the subset of Verilog to the input language of the SMV model-checker. Experiments show that this approach is able to verify complete cell libraries.

  • 110.
    Taromirad, Masoumeh
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS).
    Mousavi, Mohammad Reza
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Gray-Box Conformance Testing for Symbolic Reactive State Machines2017Inngår i: Fundamentals of Software Engineering: 7th International Conference, FSEN 2017, Tehran, Iran, April 26–28, 2017, Revised Selected Papers / [ed] Mehdi Dastani & Marjan Sirjani, Heidelberg: Springer Berlin/Heidelberg, 2017, s. 228-243Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Model-based testing (MBT) is typically a black-box testing technique. Therefore, generated test suites may leave some untested gaps in a given implementation under test (IUT). We propose an approach to use the structural and behavioural information exploited from the implementation domain to generate effective and efficient test suites. Our approach considers both specification models and implementation models, and generates an enriched test model which is used to automatically generate test suites. We show that the proposed approach is sound and exhaustive and cover both the specification and the implementation. We examine the applicability and the effectiveness of our approach by applying it to a well-known example from the railway domain. © 2017, IFIP International Federation for Information Processing.

  • 111.
    Varshosaz, Mahsa
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Al-Hajjaji, Mustafa
    Pure-Systems GmbH, Neustadt, Germany.
    Thüm, Thomas
    Technische Universität, Braunschweig, Braunschweig, Germany.
    Runge, Tobias
    Technische Universität, Braunschweig, Braunschweig, Germany.
    Mousavi, Mohammad Reza
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES). University of Leicester, Leicester, United Kingdom.
    Schaefer, Ina
    Technische Universität, Braunschweig, Braunschweig, Germany.
    A classification of product sampling for software product lines2018Inngår i: SPLC '18 Proceedings of the 22nd International Systems and Software Product Line Conference - Volume 1 / [ed] Berger et al., New York, NY: Association for Computing Machinery (ACM), 2018, s. 1-13Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The analysis of software product lines is challenging due to the potentially large number of products, which grow exponentially in terms of the number of features. Product sampling is a technique used to avoid exhaustive testing, which is often infeasible. In this paper, we propose a classification for product sampling techniques and classify the existing literature accordingly. We distinguish the important characteristics of such approaches based on the information used for sampling, the kind of algorithm, and the achieved coverage criteria. Furthermore, we give an overview on existing tools and evaluations of product sampling techniques. We share our insights on the state-of-the-art of product sampling and discuss potential future work. © 2018 Association for Computing Machinery.

  • 112.
    Varshosaz, Mahsa
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Beohar, Harsh
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Mousavi, Mohammad Reza
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Basic Behavioral Models For Software Product Lines: Revisited2018Inngår i: Science of Computer Programming, ISSN 0167-6423, E-ISSN 1872-7964, Vol. 168, s. 171-185Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In Beohar et al. (2016) [9], we established an expressiveness hierarchy and studied the notions of refinement and testing for three fundamental behavioral models for software product lines. These models were featured transition systems, product line labeled transition systems, and modal transition systems. It turns out that our definition of product line labeled transition systems is more restrictive than the one introduced by Gruler, Leucker, and Scheidemann. Adopting the original and more liberal notion changes the expressiveness results, as we demonstrate in this paper. Namely, we show that the original notion of product line labeled transition systems and featured transition systems are equally expressive. As an additional result, we show that there are featured transition systems for which the size of the corresponding product line labeled transition system, resulting from any sound encoding, is exponentially larger than the size of the original model. Furthermore, we show that each product line labeled transition system can be encoded into a featured transition system, such that the size of featured transition system is linear in terms of the size of the corresponding model. To summarize, featured transition systems are equally expressive as, but exponentially more succinct than, product line labeled transition systems. © 2018 Elsevier B.V.

  • 113.
    Varshosaz, Mahsa
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Beohar, Harsh
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Mousavi, Mohammad Reza
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Delta-Oriented FSM-Based Testing2015Inngår i: Formal Methods and Software Engineering: 17th International Conference on Formal Engineering Methods, ICFEM 2015, Paris, France, November 3-5, 2015, Proceedings / [ed] Michael Butler, Sylvain Conchon & Fatiha Zaïdi, Cham: Springer, 2015, Vol. 9407, s. 366-381Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We use the concept of delta-oriented programming to organize FSM-based test models in an incremental structure. We then exploit incremental FSM-based testing to make efficient use of this high-level structure in generating test cases. We show how our approach can lead to more efficient test-case generation, both by analyzing the complexity of the test-case generation algorithm and by applying the technique to a case study. © Springer International Publishing Switzerland 2015

  • 114.
    Vishal, Vivek
    et al.
    Philips Healthcare, Best, Netherlands.
    Kovacioglu, Mehmet
    Philips Healthcare, Best, Netherlands.
    Kherazi, Rachid
    Philips Healthcare, Best, Netherlands.
    Mousavi, Mohammad Reza
    Eindhoven University of Technology, Eindhoven, Netherlands.
    Integrating Model-Based and Constraint-Based Testing Using SpecExplorer2012Inngår i: Proceedings of the 4th Workshop on Model-based Testing in Practice (MoTiP 2012), Piscataway, N.J.: IEEE Press, 2012, s. 219-224Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We report on our experience with model-based testing using SpecExplorer within the Flat X-Ray Detection (FXD) Department of Philips Healthcare. Our initial experiments showed a practical obstacle in combining traditional functional testing techniques with model-based testing using SpecExplorer. We overcome this obstacle by specifying the constraints on our data domain in a spreadsheet and interfacing SpecExplorer with a constraint solver in order to generate concrete test data for the behavioral specifications. We report on some empirical results obtained from our experiments. © 2012 IEEE.

  • 115.
    Woehrle, Matthias
    et al.
    Embedded Software Group, Delft University of Technology, Netherlands.
    Bakhshi, Rena
    Vrije Universiteit Amsterdam, Department of Computer Science, Netherlands.
    Mousavi, Mohammad Reza
    Embedded Software Group, Delft University of Technology, Netherlands.
    Mechanized Extraction of Topology Anti-patterns in Wireless Networks2012Inngår i: Proceedings of the 9th International Conference on Integrated Formal Methods (iFM 2012), Berlin: Springer Berlin/Heidelberg, 2012, Vol. 7321, s. 158-173Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Exhaustive and mechanized formal verification of wireless networks is hampered by the huge number of possible topologies and the large size of the actual networks. However, the generic communication structure in such networks allows for reducing the root causes of faults to faulty (sub-)topologies, called anti-patterns, of small size. We propose techniques to find such anti-patterns using a combination of model-checking and automated debugging. We apply the proposed technique on two well-known protocols for wireless sensor networks and show that the techniques indeed find the root causes in terms of canonical topologies featuring the fault. © 2012 Springer-Verlag.

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