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  • 101.
    Uhlemann, Elisabeth
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Rasmussen, Lars K.
    Chalmers, Göteborg.
    Wiberg, Per-Arne
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Wireless Real-Time Communication Using Deadline Dependent Coding2006In: ARTES - A network for Real-Time research and graduate Education in Sweden 1997-2006: MRTC report (197/2006), Uppsala: Department of Information Technology, Uppsala university , 2006, p. 239-256Chapter in book (Other (popular science, discussion, etc.))
    Abstract [en]

    The constant evolution of wireless communication, and all the applications this enables, is rapidly increasing our demands on the performance of communication networks. As the transmission speed increases, entirely new applications and services, like for example video streaming, suddenly becomes interesting for wireless systems as well. The expectations of the general user with respect to performance of wireless applications are guided by the current quality of traditional wireline systems. This naturally implies a considerable challenge when designing wireless communication systems. Many of these new wireless applications are based on packet transmissions and are sub ject to time-critical constraints. The ob jective of the deadline dependent coding (DDC) communication protocol presented here is therefore to develop an efficient and fault tolerant real-time link layer foundation, enabling critical deadline dependent communication over unreliable wireless channels.

  • 102.
    Uhlemann, Elisabeth
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Wiberg, Per-Arne
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Aulin, Tor M.
    Chalmers University of Technology, Gothenburg, Sweden.
    Rasmussen, Lars R.
    Chalmers University of Technology, Gothenburg, Sweden.
    Deadline dependent coding-a framework for wireless real-time communication2000In: Seventh International Conference on Real-Time Computing Systems and Applications: proceedings : 12-14 December, 2000, Cheju Island, South Korea, Piscataway, NJ: IEEE, 2000, p. 135-142, article id 896381Conference paper (Refereed)
    Abstract [en]

    A framework for real-time communication over a wireless channel is proposed. The concept of deadline dependent coding (DDC), previously suggested by the authors, is further developed using soft decision decoding of block codes to maximize the probability of delivering information before a given deadline. The strategy of DDC is to combine different coding and decoding methods with automatic repeat request (ARQ) in order to fulfil the application requirements. These requirements are formulated as two Quality of Service (QoS) parameters: deadline (t_DL) and probability of correct delivery before the deadline (P_d), leading to a probabilistic view of real-time communication. An application can negotiate these QoS parameters with the DDC protocol, thus creating a flexible and dependable scheme.

  • 103.
    Uhlemann, Elisabeth
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Willig, Andreas
    Technical University of Berlin.
    Hard decision packet combining methods for industrial wireless relay networks2008In: Second International Conference on Communications and Electronics, 2008. ICCE 2008, Piscataway, N.J.: IEEE Press, 2008, p. 104-108Conference paper (Refereed)
    Abstract [en]

    We consider wireless relay networks for use in industrial applications with strict requirements on both reliable and timely communications. In most cases commercially available transceivers must be used, which implies that only hard decision detector outputs are available. Since relay networks typically use retransmissions of erroneous packets, packet combining methods have the potential to increase the information reliability without excessive delay. We evaluate three different hard decision packet combining methods for different placement of the source, the relay node and the destination. Packet combining can in general be improved with knowledge of the current channel state information, which, however, is often not available. In this paper we find a packet combining method which does not use channel state information but which delivers similar performance as the scheme that has knowledge of the channel state.

  • 104.
    Uhlemann, Elisabeth
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Willig, Andreas
    Technical University of Berlin.
    Joint design of relay and packet combining schemes for wireless industrial networks2008In: 2008 IEEE 67th Vehicular Technology Conference-spring: Marina Bay, Singapore, 11-14 May 2008, Piscataway, N.J.: IEEE Press, 2008, p. 2441-2445Conference paper (Refereed)
    Abstract [en]

    Wireless industrial networks differ in many respects from other types of wireless networks. In particular, since many applications impose tight real-time and reliability requirements at the same time, and packet sizes tend to be small. In this paper we design a simple and practically implementable protocol in which relaying and packet combining work together to improve the probability that packets are delivered within a prescribed deadline over fading channels. The results indicate that such a combination can be fruitfully employed in wireless industrial networks.

  • 105.
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    High-level programming of coarse-grained reconfigurable architectures2009In: 19th International Conference on Field Programmable Logic and Applications: (FPL), proceedings, Prague, Czech Republic, August 31-September 2, 2009 / [ed] Martin Daněk, Jiři Kadlec and Brent Nelson, Piscataway, N.J.: IEEE , 2009, p. 713-714Conference paper (Refereed)
    Abstract [en]

    We propose that, in order to meet high computational demands, the application development has to be based on suitable models of computations that will lead to scalable and reusable implementations. The models should enhance the understanding of the application and at the same time enable the developer to organize the computations so that they can be efficiently mapped to the target reconfigurable architecture. The goal of the thesis is to propose methods to program future coarse-grained reconfigurable architecttures in a productive manner in such a way as to achieve energy efficient mapping with improved performance.

  • 106.
    Ul-Abdin, Zain
    et al.
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing2009In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 33, no 3, p. 161-178Article in journal (Refereed)
    Abstract [en]

    In order to meet the increased computational demands of, e.g., multimedia applications, such as video processing in HDTV, and communication applications, such as baseband processing in telecommunication systems, the architectures of reconfigurable devices have evolved to coarse-grained compositions of functional units or program controlled processors, which are operated in a coordinated manner to improve performance and energy efficiency. In this survey we explore the field of coarse-grained reconfigurable computing on the basis of the hardware aspects of granularity, reconfigurability, and interconnection networks, and discuss the effects of these on energy related properties and scalability. We also consider the computation models that are being adopted for programming of such machines, models that expose the parallelism inherent in the application in order to achieve better performance. We classify the coarse-grained reconfigurable architectures into four categories and present some of the existing examples of these categories. Finally, we identify the emerging trends of introduction of asynchronous techniques at the architectural level and the use of nano-electronics from technological perspective in the reconfigurable computing discipline.

  • 107.
    Wang, Yan
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    A Language-Based Approach to Protocol Stack Implementation in Embedded Systems2009Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Embedded network software has become increasingly interesting for both researchand business as more and more networked embedded systems emerge.Well-known infrastructure protocol stacks are reimplemented on new emergingembedded hardware and software architectures. Also, newly designed orrevised protocols are implemented in response to new application requirements.However, implementing protocol stacks for embedded systems remains a timeconsumingand error-prone task due to the complexity and performance-criticalnature of network software. It is even more so when targeting resource constrainedembedded systems: implementations have to minimize energy consumption,memory usage and so on, while programming efficiency is needed toimprove on time-to-market, scalability, maintainability and product evolution.Therefore, it is worth researching on how to make protocol stack implementationsfor embedded systems both easier and more likely to be correct withinthe resource limits.In the work we present in this thesis, we take a language-based approachand aim to facilitate the implementation of protocol stacks while realizingperformance demands and keeping energy consumption and memory usagewithin the constraints imposed by embedded systems. Language technologyin the form of a type system, a runtime system and compiler transformationscan then be used to generate efficient implementations. We define a domainspecificembedded language (DSEL), Implementation of Protocol Stacks (IPS),for declaratively describing overlaid protocol stacks. In IPS, a high-level packetspecification is dually compiled into an internal data representation for protocollogic implementation, and packet processing methods which are thenintegrated into the dataflow framework of a protocol overlay specification.IPS then generates highly portable C code for various architectures from thissource. We present the compilation framework for generating packet processingand protocol logic code, and a preliminary evaluation of our compiled code.

  • 108.
    Wang, Yan
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Gaspes, Veronica
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    A Domain Specific Approach to Network Software Architecture: Assuring Conformance Between Architecture and Code2009In: Fourth International Conference on Digital Telecommunications, 2009. ICDT '09, Piscataway, N.J.: IEEE Press, 2009, p. 127-132Conference paper (Refereed)
    Abstract [en]

    Network software is typically organized according toa layered architecture that is well understood. However, writingcorrect and efficient code that conforms with the architecture stillremains a problem. To overcome this problem we propose to usea domain specific language based approach. The architecturalconstraints are captured in a domain specific notation that can beused as a source for automatic program generation. Conformancewith the architecture is thus assured by construction. Knowledgefrom the domain allows us to generate efficient code. In addition,this approach enforces reuse of both code and designs, one ofthe major concerns in software architecture. In this paper, weillustrate our approach with PADDLE, a tool that generates packetprocessing code from packet descriptions. To describe packets weuse a domain specific language of dependent types that includespacket overlays. From the description we generate C librariesfor packet processing that are easy to integrate with other partsof the code. We include an evaluation of our tool.

  • 109.
    Wang, Yan
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Gaspes, Veronica
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    A Library for Processing Ad hoc Data in Haskell: Embedding a Data Description Language2011In: Implementation and application of functional languages / [ed] Scholz, SB; Chitil, O, Springer, 2011, , p. 16p. 174-191Conference paper (Refereed)
    Abstract [en]

    Ad hoc data formats, i.e. semistructured non-standard dataformats, are pervasive in many domains that need software tools—bioinformatics,demographic surveys, geophysics and network software are justa few. Building tools becomes easier if parsing and other standard inputoutputprocessing can be automated. Modern approaches for dealingwith ad hoc data formats consist of domain specific languages based ontype systems. Compilers for these languages generate data structures andparsing functions in a target programming language in which tools andapplications are then written. We present a monadic library in Haskellthat implements a data description language. Using our library, Haskellprogrammers have access to data description primitives that can be usedfor parsing and that can be integrated with other libraries and applicationprograms without the need of yet another compiler.

  • 110.
    Wecksten, Mattias
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    RealLife - en tekniköversikt2008Report (Other academic)
    Abstract [sv]

    RealLife är en sammankopplink mellan användarens plattform och tjänsteleverantörer via en central databas. Tanken är att en individidentifierare, UBI passport, ska vara kärnan i systemet som möjliggör att flytta innehåll från plattform till plattform. Genom att ta kontroll över den databas som samlar allt material och alla tjänster får man möjlighet att sälja extremfokuserad reklam. All den teknik som krävs för att genomföra projektet RealLife finns tillgänglig i någon form redan idag. Avgörande blir om man lyckas att göra så att användaren känner någon nytta utöver vad man skulle ha fått från en traditionell söktjänst. Detta kräver articifiell intelligens utöver vad som är tillgängligt idag.

  • 111.
    Wecksten, Mattias
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Jonsson, Magnus
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Less pessimistic worst-case delay analysis for packet-switched networks2008In: IEEE International Conference on Emerging Technologies and Factory Automation, 2008. ETFA 2008, Piscataway, N.J.: IEEE Press, 2008, p. 1213-1219Conference paper (Refereed)
    Abstract [en]

    The rapid growth of distributed real-time systems creates a need for cheap and available network solutions while still fulfilling the real-time requirements. In this paper we propose a method for less pessimistic delay analysis for packet switched first come first serve network, when knowing the intervals of possible message generation. Experiments show that the proposed method generates the expected results according to theoretical limitations of the experiment cases. The experiments also show that the proposed method could be practically used for non-trivial systems. Suggestions are given for future work on how to relax traffic requirements and how to cope with circular dependencies.

  • 112.
    Weckstén, Mattias
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Jonsson, Magnus
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Vasell, Jonas
    Generic Systems Sweden AB, Stockholm, Sweden.
    Derivation of implementation constraints – implementation simulation and treatment of multiple design choices2007In: Proc. of the 9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden – RTiS’07), Västerås, Sweden, Aug. 21-22, 2007, p. 21-28Conference paper (Refereed)
    Abstract [en]

    The industrial use of ad hoc implementation methods for non-functional constrained tasks has resulted in unnecessary expensive projects. In some cases, ad hoc methods result in overly many iterations to be made and in some severe cases, total project breakdown. To be able to solve these problems a method has been developed to derive end-to-end non-functional constraints, such as timing requirements, to task-level constraints and to promote this information to the implementation phase of the project. For a tool, as the one described above, to be really useful it is important to be able to show that there is a potential cost reduction to be made. To be able to show that a certain implementation method costs less in work hours than to use an ad hoc implementation method, a model for implementation simulation with support for multiple implementation alternatives has been developed. The experiments show that using the budget based implementation method leads to a significant cost reduction in most cases, compared to the ad hoc method. As far as we know, no similar experiments has been done to compare implementation methods.

  • 113.
    Weckstén, Mattias
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Vassell, Jonas
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Jonsson, Magnus
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    A tool for derivation of implementation constraints: – evaluation using implementation simulation2004In: RTSS 2004 WIP Proceedings, The 25th IEEE International Real-Time Systems Symposium, IEEE , 2004, p. 4-Conference paper (Refereed)
    Abstract [en]

    The industrial use of ad hoc implementation methods for non-functional constrained tasks has sometimes resulted in unnecessary expensive projects. In some cases, ad hoc methods result in overly many iterations to be made and in some severe cases, total project breakdown. To be able to solve these problems a new method has been developed to derive end-to-end non-functional constraints, such as performance or resource utilization requirements, to task-level constraints and to promote this information to the implementation phase of the project. For a tool to be really useful it is important to be able to show the usability and potential cost reduction. To be able to show that a certain implementation method costs less in work hours than to use an ad hoc implementation method, a model for implementation simulation has been developed. As far as we know, no similar experiments has been done to compare implementation methods.

  • 114.
    Willig, Andreas
    et al.
    Department of Computer Science and Software Engineering, University of Canterbury, Christchurch, New Zealand.
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Deadline-Aware Scheduling of Cooperative Relayers in TDMA-Based Wireless Industrial Networks2014In: Wireless networks, ISSN 1022-0038, E-ISSN 1572-8196, Vol. 20, no 1, p. 73-88Article in journal (Refereed)
    Abstract [en]

    In this paper we consider a scenario in which a set of source nodes wishes to transmit real-time data packets periodically to a central controller over lossy wireless links, while using a TDMA-based medium access control protocol. Furthermore, a number of relay nodes are present which can help the source nodes with packet retransmissions. The key question we consider in this paper is how to schedule the TDMA slots for retransmissions while taking advantage of the relay nodes, so that the average number of packets missing their deadlines is minimized. We provide a problem formulation for the general deadline-aware TDMA relay scheduling problem. Since the design space of the general problem is large, we also present one particular class of restricted TDMA relay scheduling problems. We suggest and numerically investigate a range of algorithms and heuristics, both optimal and suboptimal, of the restricted scheduling problem, which represent different trade-offs between achievable performance and computational complexity. Specifically, we introduce two different Markov Decision Process (MDP) based formulations for schedule computation of the restricted TDMA relay scheduling problem. One MDP formulation gives an optimal schedule, another (approximate) formulation gives a sub-optimal schedule which, however, comes very close to the optimal performance at much more modest computational and memory costs. © 2013 Springer Science+Business Media New York.

  • 115.
    Willig, Andreas
    et al.
    University of Canterbury, Christchurch, New Zealand.
    Uhlemann, Elisabeth
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    On relaying for wireless industrial communications: Is careful placement of relayers strictly necessary?2012In: IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS, Piscataway, NJ: IEEE Press, 2012, p. 191-200, article id 6242567Conference paper (Refereed)
    Abstract [en]

    Relaying is a very promising technique to improve the reliability of data transmission in wireless (industrial) networks. With relaying, relay nodes support source nodes in carrying out retransmissions. A common assumption is that relayers should be placed at “good” positions (e.g. in the middle between source and destination) to achieve benefits. In this paper we tackle the question of whether it is strictly necessary to place relayers at “good” positions (which often requires extensive measurements). We present results indicating that the benefits of relaying are achievable even with randomly placed relayers, as long as enough of them are deployed. Specifically, we present results suggesting that with a sufficient (and still not too high) number of randomly deployed relayers, the probability that all packets, sent by source nodes to a central controller in a TDMA round, reach the controller is larger than for the case with source-only retransmissions. This finding holds true both in the absence and the presence of feedback. © 2012 IEEE.

  • 116.
    Willig, Andreas
    et al.
    Technische Universitt Berlin, Berlin, Germany.
    Uhlemann, Elisabeth
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    PRIOREL-COMB: A protocol framework supporting relaying and packet combining forwireless industrial networking2008In: WFCS 2008: 2008 IEEE International Workshop on Factory Communication Systems : proceedings : May 21st-23rd, 2008, Steigenberger Hotel de Saxe, Dresden, Germany / [ed] Gianluca Cena and Françoise Simonot-Lion, Piscataway, NJ: IEEE Press, 2008, p. 45-54Conference paper (Refereed)
    Abstract [en]

    The PRIOREL-COMB framework presented here integrates support for relaying and packet combining into wireless industrial networks. The selection of suitable relay nodes is made using distributed algorithms which includes different eligibility tests as well as different priority assignments. The framework improves performance in terms of probability to successfully deliver packets before their deadline and it can be implemented on top of commercial transceivers without modification of the physical layer. This class of protocols will therefore be a valuable addition to future wireless industrial communication systems.

  • 117.
    Wu, Jinfeng
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Lv, Gaofei
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Evaluation of Multicore Cache Architecture for Radar Signal Processing2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
  • 118.
    Zain-ul-Abdin,
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Compiling Stream-Language Applications to a Reconfigurable Array Processor2005In: ERSA'05: proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA, June 27-30, 2005 / [ed] Toomas P. Plaks and R. DeMara, Las Vegas: CSREA Press, 2005, p. 274-275Conference paper (Refereed)
  • 119.
    Zain-ul-Abdin,
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
    Specifying Run-time Reconfiguration in Processor Arrays using High-level language2010In: WRC 2010: 4th HiPEAC Workshop on Reconfigurable Computing, Pisa, 2010, p. 1-10Conference paper (Refereed)
    Abstract [en]

    The adoption of run-time reconfigurable parallel architectures for high-performance embedded systems is constrained by the lackof a unified programming model which can express both parallelism and reconfigurability. We propose to program an emerging class of reconfigurable processor arrays by using the programming model of occam-pi and describe how the extensions of channel direction specifiers, mobile data, dynamic process invocation, and process placement attributes can be used to express run-time reconfiguration in occam-pi. We present implementations of DCT algorithm to demonstrate the applicability of occam-pi to express reconfigurability. We concluded that occam-pi appears to be a suitable programming model for programming run-time reconfigurable processor arrays.

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