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  • 1.
    Fragal, Vanderson Hafemann
    et al.
    University of Sao Paulo, Sao Carlos, Brazil.
    Simao, Adenilso
    University of Sao Paulo, Sao Carlos, Brazil.
    Endo, Andre Takeshi
    Federal University of Paraná, Curitiba, Paraná, Brazil.
    Mousavi, Mohammad Reza
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Reducing the Concretization Effort in FSM-Based Testing of Software Product Lines2017In: 10th IEEE International Conference on Software Testing, Verification and Validation Workshops - ICSTW 2017 / [ed] Randall Bilof, Los Alamitos, CA: IEEE , 2017, p. 329-336Conference paper (Refereed)
    Abstract [en]

    To test a Software Product Line (SPL), the test artifacts and the techniques must be extended to support variability. In general, when new SPL products are developed, more tests are generated to cover new or modified features. A dominant source of extra effort for such tests is the concretization of newly generated tests. Thus, minimizing the amount of new non-concretized tests required to perform conformance testing on new products reduces the overall test effort. In this paper, we propose a test reuse strategy for conformance testing of SPL products that aims at reducing test effort. We use incremental test generation methods based on finite state machines (FSMs) to maximize test reuse. We combine these methods with a selection algorithm used to identify non-redundant concretized tests. We illustrate our strategy using examples and a case study with an embedded mobile SPL. The results indicate that our strategy can save up to 36% of test effort in comparison to current test reuse strategies for the same fault detection capability. © 2017 IEEE.

  • 2.
    Fragal, Vanderson Hafemann
    et al.
    University of São Paolo, São Carlos, Brazil.
    Simao, Adenilso
    University of São Paolo, São Carlos, Brazil.
    Mousavi, Mohammad Reza
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Validated Test Models for Software Product Lines: Featured Finite State Machines2016In: Formal Aspects of Component Software: 13th International Conference, FACS 2016, Besançon, France, October 19-21, 2016, Revised Selected Papers / [ed] Kouchnarenko, Olga & Khosravi, Ramtin, Cham: Springer, 2016, Vol. 10231, p. 210-227Conference paper (Refereed)
    Abstract [en]

    Variants of the finite state machine (FSM) model have been extensively used to describe the behaviour of reactive systems. In particular, several model-based testing techniques have been developed to support test case generation and test case executions from FSMs. Most such techniques require several validation properties to hold for the underlying test models. In this paper, we propose an extension of the FSM test model for software product lines (SPLs), named featured finite state machine (FFSM). As the first step towards using FFSMs as test models, we define feature-oriented variants of basic test model validation criteria. We show how the high-level validation properties coincide with the necessary properties on the product FSMs. Moreover, we provide a mechanised tool prototype for checking the feature-oriented properties using satisfiability modulo theory (SMT) solver tools. We investigate the applicability of our approach by applying it to both randomly generated FFSMs as well as those from a realistic case study (the Body Comfort System). The results of our study show that for random FFSMs over 16 independent non-mandatory features, our technique provides substantial efficiency gains for the set of proposed validity checks. © Springer International Publishing AG 2017

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