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  • 1.
    Garcia, Alejandro
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Johansson, Lisbeth
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Weckstén, Mattias
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Guaranteed periodic real-time communication over wormhole switched networks2000Ingår i: Parallel and distributed computing systems: proceedings of the ISCA 13th international conference, Las Vegas, Nevada, USA, August 8 - 10, 2000 / [ed] Ghulam Chaudhry; Edwin Sha, Raleigh, NC: INTERNATIONAL SOCIETY COMPUTERS & THEIR APPLICATIONS (ISCA) , 2000, s. 632-639Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper, we investigate how to efficiently implement TDMA (Time Division Multiple Access) on a wormhole switched network using a pure software solution in the end nodes. Transmission is conflict free on the time-slot level and hence deadlock free. On the sub- slot level, however, conflicts are possible when using early sending, a method we propose in order to reduce latency while still not hazarding the TDMA schedule. We propose a complete system to offer services for dynamic establishment of guaranteed periodic real-time virtual channels. Two different clock synchronization approaches for integration into the TDMA system are discussed. Implementation and experimental studies have been done on a cluster of PCs connected by a Myrinet network. Also, a case study with a radar signal processing application is presented to show the usability. A best-case reduction of the latency of up to 37 percent for 640 Byte messages by using early sending in Myrinet is shown in the case study. Source routed wormhole switching networks are assumed in the work but the results are applicable on some other categories of switched networks too.

  • 2.
    Kunert, Kristina
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Weckstén, Mattias
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Algorithm for the choice of topology in reconfigurable networks with real-time support2007Rapport (Övrigt vetenskapligt)
    Abstract [en]

    Many future embedded systems are likely to contain System-on-Chip solutions with on-chip networks, and to achieve high aggregated throughputs in these networks, a switched topology can be used. For further performance improvements, the topology can be adapted to application demands, either when designing the chip or by run-time reconfiguration between different predefined application modes. In this report, we describe an algorithm for the choice of topology in, e.g., packet-switched on-chip networks, considering the real-time demands in terms of throughput and delay often put on such systems. To further address possible real-time demands, we include a feasibility analysis to check that the application, when mapped onto the system, will behave in line with its real-time demands. With input information about the traffic characteristics, our algorithm creates a topology and generates routing information for all logical traffic channels. In a case study, we show that our algorithm results in a topology that can outperform the use of state of the art topologies for high-performance computer architectures. Although we have targeted for reconfigurable Network-on-Chip architectures, the algorithm can also be used for other systems. Our algorithm gives the opportunity for topology choice at design stage, both for static network topologies and for reconfigurable network topologies that can be reconfigured during run-time.

  • 3.
    Kunert, Kristina
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Weckstén, Mattias
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Algorithm for the choice of topology in reconfigurable on-chip networks with real-time support2007Ingår i: Proceedings of the 2nd international conference on Nano-Networks, Bryssels: ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering) , 2007, s. 1-7Konferensbidrag (Refereegranskat)
    Abstract [en]

    Many future embedded systems are likely to contain System-on-Chip solutions with on-chip networks and in order to achieve high aggregated throughputs in these networks, a switched topology can be used. For further performance improvements, the topology can be adapted to application demands, either when designing the chip or by run-time reconfiguration between different predefined application modes. In this paper, we present an algorithm for the choice of topology in, e.g., on-chip networks, considering realtime demands in terms of throughput and delay often put on such systems. To further address possible real-time demands, we include a feasibility analysis to check that the application, when mapped onto the system, will behave in line with its real-time demands. With input information about traffic characteristics, our algorithm creates a topology and generates routing information for all logical traffic channels. In a case study, we show that our algorithm results in a topology that can outperform the use of state of the art topologies for high-performance computer architectures.

  • 4.
    Vaske, Camilla
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi.
    Weckstén, Mattias
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS).
    Järpe, Eric
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), CAISR Centrum för tillämpade intelligenta system (IS-lab).
    Velody — A novel method for music steganography2017Ingår i: 2017 3rd International Conference on Frontiers of Signal Processing (ICFSP 2017): September 6-8, 2017, Paris, France, Institute of Electrical and Electronics Engineers (IEEE), 2017, s. 15-19Konferensbidrag (Refereegranskat)
    Abstract [en]

    This study describes a new method for musical steganography utilizing the MIDI format. MIDI is a standard music technology protocol that is used around the world to create music and make it available for listening. Since no publicly available method for MIDI steganography has been found (even though there are a few methods described in the literature), the study investigates how a new algorithm for MIDI steganography can be designed so that it satisfies capacity and security criteria. As part of the study, a method for using velocity values to hide information in music has been designed and evaluated, during which the capacity of the method is found to be comparable with similar methods. In an audibility test, it is observed that audible impact on the music can not be distinguished at any reasonable significance level, which means that also a security criterion is met. © 2017 IEEE.

  • 5.
    Wecksten, Mattias
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    RealLife - en tekniköversikt2008Rapport (Övrigt vetenskapligt)
    Abstract [sv]

    RealLife är en sammankopplink mellan användarens plattform och tjänsteleverantörer via en central databas. Tanken är att en individidentifierare, UBI passport, ska vara kärnan i systemet som möjliggör att flytta innehåll från plattform till plattform. Genom att ta kontroll över den databas som samlar allt material och alla tjänster får man möjlighet att sälja extremfokuserad reklam. All den teknik som krävs för att genomföra projektet RealLife finns tillgänglig i någon form redan idag. Avgörande blir om man lyckas att göra så att användaren känner någon nytta utöver vad man skulle ha fått från en traditionell söktjänst. Detta kräver articifiell intelligens utöver vad som är tillgängligt idag.

  • 6.
    Wecksten, Mattias
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Resource budgeting as a tool for reduced development cost for embedded real-time computer systems2004Licentiatavhandling, monografi (Övrigt vetenskapligt)
    Abstract [en]

    Wouldn’t it be great if there were a systematic method for derivation of non functional constraints available at design time that made it possible to verify design and make implementa tion a much clearer task? This kind of methods are needed since systems of increasing com plexity has to be developed, and the cost for failing has proven to bee too high. The problem is how to derive the design time constraints into implementation time constraints, maintaining the traceability for the individual constraints, and early on get indications whether a project is about to fail or not.A method for implementation time constraint derivation has been developed and is presented in this thesis. Along with the basic method, several extensions are proposed. Evaluations of the practical usefulness of the method and the method’s scalability have been done. To prove the method’s importance in real development projects, a method for evaluation of the usability of this kind of methods has also been developed. The evaluation of the practicality shows that it is possible to find close to optimal solutions (within percent) in short time (within minutes). The evaluation of the scalability shows that the run time for finding implementable solutions scales polynomial with the size of the task graph. The evaluation of the usability shows that using the proposed method always leads to lower development cost than using an ad hoc method, in the case that the implementation is about to fail.

  • 7.
    Wecksten, Mattias
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Är du beredd? – för nu snor någon dina företagshemligheter!2008Ingår i: Hallands Affärer, nr 3, s. 1-Artikel i tidskrift (Övrig (populärvetenskap, debatt, mm))
    Abstract [sv]

    Populärvetenskapligt brandtal om nyttan och behovet av välutbildade nätverkstekniker med perspektiv på såväl teknik som juridik.

  • 8.
    Wecksten, Mattias
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Less pessimistic worst-case delay analysis for packet-switched networks2008Ingår i: IEEE International Conference on Emerging Technologies and Factory Automation, 2008. ETFA 2008, Piscataway, N.J.: IEEE Press, 2008, s. 1213-1219Konferensbidrag (Refereegranskat)
    Abstract [en]

    The rapid growth of distributed real-time systems creates a need for cheap and available network solutions while still fulfilling the real-time requirements. In this paper we propose a method for less pessimistic delay analysis for packet switched first come first serve network, when knowing the intervals of possible message generation. Experiments show that the proposed method generates the expected results according to theoretical limitations of the experiment cases. The experiments also show that the proposed method could be practically used for non-trivial systems. Suggestions are given for future work on how to relax traffic requirements and how to cope with circular dependencies.

  • 9.
    Wecksten, Mattias
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Vasell, Jonas
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Towards a tool for derivation of implementation constraints2004Ingår i: Ninth IEEE International Conference on Engineering Complex Computer Systems, 2004. Proceedings, Piscataway, N.J.: IEEE , 2004, s. 119-127Konferensbidrag (Refereegranskat)
    Abstract [en]

    An increasing concern in the development of embedded systems is that fundamental design problems often remain undetected until the final tests, after implementation and integration of all components, or maybe even later - at runtime. This is particularly important when it comes to meeting nonfunctional constraints such as performance or resource utilization requirements. Correcting problems with their sources in design, after implementation, may be very costly as it often requires both redesign and re-implementation. Therefore, much effort has been put into the development of methods and tools that help system designers and developers to detect problems as early as possible during system development. This paper contributes with an addition to that field by presenting and evaluating the practical usefulness of a method that makes it possible to detect problems in system design and dimensioning, even before all components of the system have been fully implemented. Evaluation of the proposed method has been done through 17 different case studies with different characteristics, focusing particularly on realtime latency requirements for tasks on homogeneous single bus platforms. The evaluation indicates a practical method that can be turned into a powerful tool. The presented principles can be extended to wider classes of constraints and systems.

  • 10.
    Weckstén, Mattias
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS).
    Frick, Jan
    Högskolan i Halmstad.
    Sjostrom, Andreas
    Högskolan i Halmstad.
    Järpe, Eric
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), CAISR Centrum för tillämpade intelligenta system (IS-lab).
    A Novel Method for Recovery from Crypto Ransomware Infections2016Ingår i: 2016 2nd IEEE International Conference on Computer and Communications, ICCC 2016 - Proceedings, New York: IEEE, 2016, s. 1354-1358Konferensbidrag (Refereegranskat)
    Abstract [en]

    Extortion using digital platforms is an increasing form of crime. A commonly seen problem is extortion in the form of an infection of a Crypto Ransomware that encrypts the files of the target and demands a ransom to recover the locked data. By analyzing the four most common Crypto Ransomwares, at writing, a clear vulnerability is identified; all infections rely on tools available on the target system to be able to prevent a simple recovery after the attack has been detected. By renaming the system tool that handles shadow copies it is possible to recover from infections from all four of the most common Crypto Ransomwares. The solution is packaged in a single, easy to use script. © 2016 IEEE.

  • 11.
    Weckstén, Mattias
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Vasell, J.
    Generic Systems Sweden AB.
    Derivation of implementation constraints - implementation simulation and treatment of multiple design choices2005Ingår i: Proceedings: 10th IEEE International Conference on Engineering of Complex Computer Systems, ICECCS 2005, 16-20 June 2005, Shanghai, China, Los Alamitos, Calif.: IEEE Computer Society, 2005, s. 459-466Konferensbidrag (Refereegranskat)
    Abstract [en]

    The industrial use of ad hoc implementation methods for non-functional constrained tasks has resulted in unnecessary expensive projects. In some cases, ad hoc methods result in overly many iterations to be made and in some severe cases, total project breakdown. To be able to solve these problems a method has been developed to derive end-to-end non-functional constraints, such as timing requirements, to task-level constraints and to promote this information to the implementation phase of the project. For a tool, as the one described above, to be really useful it is important to be able to show that there is a potential cost reduction to be made. To be able to show that a certain implementation method costs less in work hours than to use an ad hoc implementation method, a model for implementation simulation with support for multiple implementation alternatives has been developed. The experiments show that using the budget based implementation method leads to a significant cost reduction in most cases, compared to the ad hoc method. As far as we know, no similar experiments have been done to compare implementation methods.

  • 12.
    Weckstén, Mattias
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Vasell, Jonas
    Generic Systems Sweden AB, Stockholm, Sweden.
    Derivation of implementation constraints – implementation simulation and treatment of multiple design choices2007Ingår i: Proc. of the 9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden – RTiS’07), Västerås, Sweden, Aug. 21-22, 2007, s. 21-28Konferensbidrag (Refereegranskat)
    Abstract [en]

    The industrial use of ad hoc implementation methods for non-functional constrained tasks has resulted in unnecessary expensive projects. In some cases, ad hoc methods result in overly many iterations to be made and in some severe cases, total project breakdown. To be able to solve these problems a method has been developed to derive end-to-end non-functional constraints, such as timing requirements, to task-level constraints and to promote this information to the implementation phase of the project. For a tool, as the one described above, to be really useful it is important to be able to show that there is a potential cost reduction to be made. To be able to show that a certain implementation method costs less in work hours than to use an ad hoc implementation method, a model for implementation simulation with support for multiple implementation alternatives has been developed. The experiments show that using the budget based implementation method leads to a significant cost reduction in most cases, compared to the ad hoc method. As far as we know, no similar experiments has been done to compare implementation methods.

  • 13.
    Weckstén, Mattias
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Vassell, Jonas
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    A tool for derivation of implementation constraints: – evaluation using implementation simulation2004Ingår i: RTSS 2004 WIP Proceedings, The 25th IEEE International Real-Time Systems Symposium, IEEE , 2004, s. 4-Konferensbidrag (Refereegranskat)
    Abstract [en]

    The industrial use of ad hoc implementation methods for non-functional constrained tasks has sometimes resulted in unnecessary expensive projects. In some cases, ad hoc methods result in overly many iterations to be made and in some severe cases, total project breakdown. To be able to solve these problems a new method has been developed to derive end-to-end non-functional constraints, such as performance or resource utilization requirements, to task-level constraints and to promote this information to the implementation phase of the project. For a tool to be really useful it is important to be able to show the usability and potential cost reduction. To be able to show that a certain implementation method costs less in work hours than to use an ad hoc implementation method, a model for implementation simulation has been developed. As far as we know, no similar experiments has been done to compare implementation methods.

1 - 13 av 13
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  • modern-language-association-8th-edition
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  • de-DE
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