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  • 1.
    Bengtsson, Jerker
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Baseband Processing in 3G UMTS Radio Base Stations2006Rapport (Annet vitenskapelig)
    Abstract [en]

    This report presents a study of functionality, service dataflows, computation characteristics and processing parameters for baseband processing in radio base stations. The study has been performed with the objective to develop a programming model that is natural and efficient to use for baseband programming and which can be efficiently compiled to parallel computing structures. In order to achieve this objective it is necessary to analyse and understand the logical architecture of the application in order to be able to define processing characteristics and thereby requirements on languages as well as on physical system architectures. Moreover, to be able to test and verify programming and mapping of functions it is necessary to have realistic but still manageable test cases. The study is focused on the third generation partnership project (3GPP) standard specifications for 3G radio base stations. The specifications cover the complete 3G network-architecture and are quite extensive and complex. To make experiments manageable, it is necessary to abstract system functionality that is not directly relevant for the RBS baseband processing. Moreover, the standard specifications only describe the required processing functionality on an abstract logical level. In this report, the functionality of the baseband functions is explained and also described using illustrations of dataflows and abstract mapping of two 3G service cases. The results of the study constitute a comprehensive description of the processing flow and the mapping of user data channels in 3G radio base stations – spanning data and control input from layer 2 to physical channel output from layer 1. Data dependencies between functions are illustrated with figures and it is concluded that these dependencies are of producer/consumer type. It is discussed how different functions can be mapped in MIMD and SIMD fashion with regard to the data dependencies, the data stream lengths and the control operations required to handle bit stream processing on word-length processor architectures.

  • 2.
    Bengtsson, Jerker
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Efficient implementation of stream applications on processor arrays2006Licentiatavhandling, med artikler (Annet vitenskapelig)
    Abstract [en]

    This thesis concludes work conducted on exploring the usage of parallel and reconfigurable processor architectures in industrial high-performance embedded systems. This kind of systems has by tradition been built using a mix of digital signal processors and custom made hardware. Digital signal processors provide full functional felxibility, but at the cost of lower performance. Custom made hardware can be optimized for specific functions for high performance, but at the cost of inflexibility and high development costs. A desire is to combine flexibility and performance using commercial hardware, without trading too much of performance for flexibility.

    Parallel and reconfigurable architectures provide a flexible computing space constituting processing elements that are coupled through configurable communication structures. Architectures designed with less complex processing elements render a high degree of utilizable parallelism at the cost of having to use a portion of the pocessing elements for control functions. In the thesis it is shown that it is possible to utilize this kind of architecture to achieve high performance efficiency, despite the fact that a large fraction of PEs are required to implement control-oriented portions in a fairly complex algorithm.

    A major problem is that architectures of this kind expose a very complex programming abstraction for compilers and programmers. The approach taken in this work is a domain-specific stream processing model which provides means to express application-specific dataflows and computations in terms of streams. An extensive application study comprising the baseband processing in radio base stations has been used to define sufficient data types, operators and language construct. Furthermore, to support industrial requirements on portability to different architectures, it must be possible to express parallelism and characteristic computations without exposing of hardware details in the source code.

    To be able to prototype and set up experiments with stream processing languages an experimental programming framework has been developed. A first prototype language with specific primitive types, operators and stream constructs has been implemented in order to elaborate with baseband programming. It is demonstrated how these types and operators can be used to express machine-independent bit field and other fine-grained data parallel computations. Furthermore, the language has been designed with constructs for efficient and flexible programming of reconfiguration of distributed function parameters.

  • 3.
    Bengtsson, Jerker
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Intermediate representations for simulation and implementation2010Inngår i: Handbook of Signal processing systems / [ed] S.S Bhattacharyya, E.F. Deprettere, R. Leupers and J. Takala, New York: Springer-Verlag New York, 2010, 1, s. 739-767Kapittel i bok, del av antologi (Annet vitenskapelig)
  • 4.
    Bengtsson, Jerker
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Models and Methods for Development of DSP Applications on Manycore Processors2009Doktoravhandling, med artikler (Annet vitenskapelig)
    Abstract [en]

    Advanced digital signal processing systems require specialized high-performance embedded computer architectures. The term high-performance translates to large amounts of data and computations per time unit. The term embedded further implies requirements on physical size and power efficiency. Thus the requirements are of both functional and non-functional nature. This thesis addresses the development of high-performance digital signal processing systems relying on manycore technology. We propose building two-level hierarchical computer architectures for this domain of applications. Further, we outline a tool flow based on methods and analysis techniques for automated, multi-objective mapping of such applications on distributed memory manycore processors. In particular, the focus is put on how to provide a means for tunable strategies for mapping of task graphs on array structured distributed memory manycores, with respect to given application constraints. We argue for code mapping strategies based on predicted execution performance, which can be used in an auto-tuning feedback loop or to guide manual tuning directed by the programmer. Automated parallelization, optimisation and mapping to a manycore processor benefits from the use of a concurrent programming model as the starting point. Such a model allows the programmer to express different types and granularities of parallelism as well as computation characteristics of importance in the addressed class of applications. The programming model should also abstract away machine dependent hardware details. The analytical study of WCDMA baseband processing in radio base stations, presented in this thesis, suggests dataflow models as a good match to the characteristics of the application and as execution model abstracting computations on a manycore. Construction of portable tools further requires a manycore machine model and an intermediate representation. The models are needed in order to decouple algorithms, used to transform and map application software, from hardware. We propose a manycore machine model that captures common hardware resources, as well as resource dependent performance metrics for parallel computation and communication. Further, we have developed a multifunctional intermediate representation, which can be used as source for code generation and for dynamic execution analysis. Finally, we demonstrate how we can dynamically analyse execution using abstract interpretation on the intermediate representation. It is shown that the performance predictions can be used to accurately rank different mappings by best throughput or shortest end-to-end computation latency.

  • 5.
    Bengtsson, Jerker
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Gaspes, Veronica
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Machine Assisted Code Generation for Manycore Processors2007Inngår i: Proceedings of the 9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden - RTiS'07), 2007, s. 9-Konferansepaper (Fagfellevurdert)
  • 6.
    Bengtsson, Jerker
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Hoang Bengtsson, Hoai
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Dynamic Real-time DSP on Manycores2010Konferansepaper (Fagfellevurdert)
  • 7.
    Bengtsson, Jerker
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    A configurable framework for stream programming exploration in baseband applications2006Inngår i: 2006 IEEE International Parallel & Distributed Processing Symposium: Rhodes Island, Greece : 25-29 April, 2006, Piscataway, N.J.: IEEE Press, 2006, s. 8-Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents a configurable framework to be used for rapid prototyping of stream based languages. The framework is based on a set of design patterns defining the elementary structure of a domain specific language for high-performance signal processing. A stream language prototype for baseband processing has been implemented using the framework. We introduce language constructs to efficiently handle dynamic reconfiguration of distributed processing parameters. It is also demonstrated how new language specific primitive data types and operators can be used to efficiently and machine independently express computations on bitfields and data-parallel vectors. These types and operators yield code that is readable, compact and amenable to a stricter type checking than is common practice. They make it possible for a programmer to explicitly express parallelism to be exploited by a compiler. In short, they provide a programming style that is less error prone and has the potential to lead to more efficient implementations.

  • 8.
    Bengtsson, Jerker
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    A domain-specic approach for software development on manycore platforms2008Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The programming complexity of increasingly parallel processors calls for new tools that assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed as part of a tool for mapping dataflow graphs onto manycores. One of the models captures the essentials of manycores identified as suitable for signal processing, and which we use as tar- get for our algorithms. As an intermediate representation we introduce timed configuration graphs, which describe the mapping of a model of an application onto a machine model. Moreover, we show how a timed configuration graph by very simple means can be evaluated using an abstract interpretation to obtain performance feedback. This infor- mation can be used by our tool and by the programmer in order to discover improved mappings.

  • 9.
    Bengtsson, Jerker
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    A Domain-specific Approach for Software Development on Manycore Platforms2008Inngår i: SIGARCH Computer Architecture News, ISSN 0163-5964, E-ISSN 1943-5851, Vol. 36, nr 5, s. 2-10Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The programming complexity of increasingly parallel processors calls for new tools that assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed as part of a tool for mapping dataflow graphs onto manycores. One of the models captures the essentials of manycores identified as suitable for signal processing, and which we use as target for our algorithms. As an intermediate representation we introduce timed configuration graphs, which describe the mapping of a model of an application onto a machine model. Moreover, we show how a timed configuration graph by very simple means can be evaluated using an abstract interpretation to obtain performance feedback. This information can be used by our tool and by the programmer in order to discover improved mappings.

  • 10.
    Bengtsson, Jerker
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Manycore performance analysis using timed configuration graphs2009Inngår i: International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09 / [ed] Michael Joseph Schulte and Walid Najjar, Piscataway, N.J.: IEEE Press, 2009, s. 108-117Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.

  • 11.
    Bengtsson, Jerker
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Methodologies and tools for development of signal processing software on multicore platforms2008Inngår i: 2008 proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture: MICRO-41, November 8-12, 2008, Lake Como, Italy, Piscataway, N.J.: IEEE Computer Society, 2008, s. 2-Konferansepaper (Fagfellevurdert)
  • 12.
    Hoang, Hoai
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Bengtsson, Jerker
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    On supporting real-time communication over the IEEE 802.15.4 protocol2008Inngår i: Proceedings of the international conference on wireless information networks and systems (WinSys 2008), Setubal: INSTICC Press, 2008, s. 82-87Konferansepaper (Fagfellevurdert)
    Abstract [en]

    IEEE 802.15.4 is a new enabling technology for low data rate wireless personal networks. This standard was not specifically designed for wireless sensor networks, but it has shown to be a good match with necessary requirements on low data rate, low power consumption and low cost. Unlike the former 802.11 standard, the MAC protocol specified in IEEE 802.15.4 can operate in two different modes: beacon-enabled mode or non-beacon enable mode. In beacon-enabled mode, nodes can exclusively allocate a number of guaranteed time slots, similar to a resource reservation scheme. Hence, the IEEE 802.15.4 MAC protocol have sufficient capabilities for supporting real-time communication. This paper presents the key features of IEEE 802.15.4 which makes it an attractive standard to use for real-time wireless sensor networks. Two real-time protocols extending the IEEE 802.15.4 standard are reviewed. The purpose of this paper is to present the state of the art on real-time support over IEEE 802.15.4 for wireless sensor networks and to discuss the possibilities on improvements on both the standard and the real-time protocols extending the standard.

  • 13.
    Johnsson, Dennis
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Bengtsson, Jerker
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Svensson, Bertil
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Two-level Reconfigurable Architecture for High-Performance Signal Processing2004Inngår i: ERSA'04, The 2004 International Conference on Engineering of Reconfigurable Systems and Algorithms: The 2004 International MultiConference in Computer Science and Computer Engineering / [ed] Toomas P. Plaks, Arthens: CSREA Press, 2004, s. 177-183Konferansepaper (Fagfellevurdert)
    Abstract [en]

    High speed signal processing is often performed as a pipeline of functions on streams or blocks of data. In order to obtain both flexibility and performance, parallel, reconfigurable array structures are suitable for such processing. The array topology can be used both on the micro and macro-levels, i.e. both when mapping a function on a fine-grained array structure and when mapping a set of functions on different nodes in a coarse-grained array. We outline an architecture on the macro-level as well as explore the use of an existing, commercial, word level reconfigurable architecture on the micro-level. We implement an FFT algorithm in order to determine how much of the available resources are needed for controlling the computations. Having no program memory and instruction sequencing available, a large fraction, 70%, of the used resources is used for controlling the computations, but this is still more efficient than having statically dedicated resources for control. Data can stream through the array at maximum I/O rate, while computing FFTs. The paper also shows how pipelining of the FFT algorithm over a two-level reconfigurable array of arrays can be done in various ways, depending on the application demands.

  • 14.
    Svensson, Bertil
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Ul-Abdin, Zain
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Ericsson, Per M.
    Saab AB (EDS), Gothenburg, Sweden.
    Åhlander, Anders
    Saab AB (EDS), Gothenburg, Sweden.
    Hoang Bengtsson, Hoai
    Viktoria Swedish ICT, Gothenburg, Sweden.
    Bengtsson, Jerker
    Saab AB (EDS), Gothenburg, Sweden.
    Gaspes, Veronica
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Nordström, Tomas
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    A Running Leap for Embedded Signal Processing to Future Parallel Platforms2014Inngår i: WISE'14: Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering, New York, NY: Association for Computing Machinery (ACM), 2014, s. 35-42Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper highlights the collaboration between industry and academia in research. It describes more than two decades of intensive development and research of new hardware and software platforms to support innovative, high-performance sensor systems with extremely high demands on embedded signal processing capability. The joint research can be seen as the run before a necessary jump to a new kind of computational platform based on parallelism. The collaboration has had several phases, starting with a focus on hardware, then on efficiency, later on software development, and finally on taking the jump and understanding the expected future. In the first part of the paper, these phases and their respective challenges and results are described. Then, in the second part, we reflect upon the motivation for collaboration between company and university, the roles of the partners, the experiences gained and the long-term effects on both sides. Copyright © 2014 ACM.

1 - 14 of 14
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