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  • 1.
    Bergenhem, Carl
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Gördén, Bengt
    SUNET/KTH-NOC.
    Åhlander, Anders
    Ericsson Microwave Systems.
    Heterogeneous real-time services in high-performance system area networks - application demands and case study definitions2002Rapport (Övrigt vetenskapligt)
    Abstract [en]

    To be able to verify the feasibility of high-performance networks, it is essential to evaluate them according to specific application requirements. At the same time, specifications of quite general, or understandable, application requirements are needed for the ability to make repeated analyses on different networks. Especially, heterogeneous real-time requirements must be defined to be able to analyze networks to be used in future applications. In this report, we introduce two application fields where system area networks (SANs) supporting heterogeneous real-time services are highly desirable if not required: radar signal processing and large IP routers. For each application field, a case study with heterogeneous real-time communication requirements is defined. No case studies are presented in this report. Instead, they are defined for later evaluations to determine how suitable networks are for applications with heterogeneous real-time communication requirements.

  • 2.
    Forsberg, Håkan
    et al.
    Department of Computer Engineering, Chalmers University of Technology, Göteborg, Sweden.
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Åhlander, Anders
    Airborne Radar Division, Ericsson Microwave Systems, Mölndal, Sweden.
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Radar signal processing using pipelined optical hypercube interconnects2001Ingår i: Proceedings of the 15th International Parallel and Distributed Processing Symposium: IPDPS 2001 : abstracts and CD-ROM, Los Alamitos, California: IEEE Computer Society Press , 2001, s. 2043-2052, artikel-id 925201Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper, we consider the mapping of two radar algorithms on a new scalable hardware architecture. The architecture consists of several computational modules that work independently and send data simultaneously in order to achieve high throughput. Each computational module is composed of multiple processors connected in a hypercube topology to meet scalability and high bisection bandwidth requirements. Free-space optical interconnects and planar packaging technology make it possible to transform the hypercubes into planes. Optical fan-out reduces the number of optical transmitters and thus the hardware cost. Two example systems are analyzed and mapped onto the architecture. One 64-channel airborne radar system with a sustained computational load of more than 1.6 TFLOPS, and one ground-based 128-channel radar system with extreme inter-processor communication demands.

  • 3.
    Johnsson, Dennis
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Åhlander, Anders
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Analyzing the Advantages of Run-Time Reconfiguration in Radar Signal Processing2005Ingår i: Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems / [ed] S. Q. Zheng, Anaheim: ACTA Press, 2005, s. 701-706Konferensbidrag (Refereegranskat)
    Abstract [en]

    Configurable architectures have emerged as one of the most powerful programmable signal processing platforms commercially available, obtaining their performance through the use of spatial parallelism. By changing the functionality of these devices during run-time, flexible mapping of signal processing applications can be made. The run-time flexibility puts requirements on the reconfiguration time that depend both on the application and on the mapping strategy. In this paper we analyze one such application, Space Time Adaptive Processing for radar signal processing, and show three different mappings and their requirements. The allowed time for run-time reconfiguration in these three cases varies from 1 ms down to 1 µs. Each has its own advantages, such as data reuse and optimization of computational kernels. Architectures with reconfiguration times in the order of 10 µs provide the flexibility needed for mapping the example in an efficient way, allowing for on-chip data reuse between the different processing stages.

  • 4.
    Jonsson, Magnus
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Svensson, Bertil
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Taveniku, Mikael
    Chalmers University of Technology.
    Åhlander, Anders
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Fiber-ribbon pipeline ring network for high-performance distributed computing systems1997Ingår i: Proceedings of the Third International Symposium on Parallel Architectures, Algorithms, and Networks, 1997. (I-SPAN '97), IEEE, 1997, s. 138-143Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper, we propose a high-bandwidth ring network built up with fiber-ribbon point-to-point links. The network has support for both packet switched and circuit switched traffic. Very high throughputs can be achieved in the network due to pipelining, i.e., several packets can be traveling through the network simultaneously but in different segments of the ring. The network can be built today using fiber-optic off-the-shelf components. The increasingly good price/performance ratio for fiber-ribbon links indicates a great success potential for the proposed kind of networks. We also present a massively parallel radar signal processing system with exceptionally high demands on the communication network. An aggregated throughput of tens of Gb/s is needed in this application, and this is achieved with the proposed network.

  • 5.
    Jonsson, Magnus
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Åhlander, Anders
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Taveniku, Mikael
    Chalmers University of Technology.
    Svensson, Bertil
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).
    Time-deterministic WDM star network for massively parallel computing in radar systems1996Ingår i: Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections: October 27-29, 1996, Maui, Hawaii / [ed] Allan Gottlieb, Los Alamitos, California: IEEE Computer Society Press , 1996, s. 85-93Konferensbidrag (Refereegranskat)
    Abstract [en]

    In massively parallel computer systems for embedded real-time applications there are normally very high bandwidth demands on the interconnection network. Other important properties are time-deterministic latency and services to guarantee that deadlines are met. In this paper we analyze how these properties vary with the design parameters for a passive optical star network, specifically when used in a massively parallel radar signal processing system. The aggregated bandwidth and computational power of the radar system are approximately 45 Gb/s and 100 GOPS, respectively. The analysis is focused on the medium access control protocol, called TD-TWDMA, for the time and wavelength multiplexed network. It is concluded that the proposed network is very well suited to this kind of signal-processing applications. We also present a new distributed slot-allocation algorithm with real-time properties.

  • 6.
    Svensson, Bertil
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Ul-Abdin, Zain
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Ericsson, Per M.
    Saab AB (EDS), Gothenburg, Sweden.
    Åhlander, Anders
    Saab AB (EDS), Gothenburg, Sweden.
    Hoang Bengtsson, Hoai
    Viktoria Swedish ICT, Gothenburg, Sweden.
    Bengtsson, Jerker
    Saab AB (EDS), Gothenburg, Sweden.
    Gaspes, Veronica
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Nordström, Tomas
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    A Running Leap for Embedded Signal Processing to Future Parallel Platforms2014Ingår i: WISE'14: Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering, New York, NY: Association for Computing Machinery (ACM), 2014, s. 35-42Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper highlights the collaboration between industry and academia in research. It describes more than two decades of intensive development and research of new hardware and software platforms to support innovative, high-performance sensor systems with extremely high demands on embedded signal processing capability. The joint research can be seen as the run before a necessary jump to a new kind of computational platform based on parallelism. The collaboration has had several phases, starting with a focus on hardware, then on efficiency, later on software development, and finally on taking the jump and understanding the expected future. In the first part of the paper, these phases and their respective challenges and results are described. Then, in the second part, we reflect upon the motivation for collaboration between company and university, the roles of the partners, the experiences gained and the long-term effects on both sides. Copyright © 2014 ACM.

  • 7.
    Taveniku, Mikael
    et al.
    Department of Computer Engineering, Chalmers University of Technology, Göteborg, Sweden & Ericsson Microwave Systems AB, Mölndal, Sweden.
    Åhlander, Anders
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    A multiple SIMD mesh architecture for multi-channel radar processing1996Ingår i: Proceedings of: ICSPAT'96, international conference on signal processing applications & technology, Boston MA, USA, October 7-10: Research report CCA (9602), Miller Freeman , 1996, s. 1421-1427Konferensbidrag (Refereegranskat)
    Abstract [en]

    In modern and future radar applications there are high demands on the signal processing chain in terms of computational power and generality. At the same time, there are hard size and power consumption constraints. This paper reports on a project whose aim is to find a good scalable computer architecture that is flexible, programmable and as general-purpose as possible without too much performance loss.

    The proposed architecture consists of multiple SIMD computing modules, each based on a number of small mesh arrays. The modules are fully programmable and work globally as a MIMD machine and locally as SIMD machines. The data network is modular and provides both high bandwidth capacity and fast response. It has a fiber-optic stars topology, and employs time and wavelength division multiplexing, together with a medium access method specially developed for real-time systems.

    In this paper, we use a radar system with 64 processing channels to illustrate the algorithms and the usage of the processor modules. We show that it is possible to use a machine, consisting of small mesh processor arrays forming larger modules, with good efficiency. The building blocks show good balance between computational power and I/O bandwidth, and the SIMD approach seems good from algorithm-mapping point of view.

  • 8.
    Taveniku, Mikael
    et al.
    Department of Computer Engineering, Chalmers University of Technology S-412 96 Goteborg, Sweden - Ericsson Microwave Systems AB, S-431 84 Molndal, Sweden .
    Åhlander, Anders
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Jonsson, Magnus
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    The VEGA moderately parallel MIMD, moderately parallel SIMD, architecture for high performance array signal processing1998Ingår i: Proceedings of the first merged International Parallel Processing Symposium & Symposium on Parallel and Distributed Processing: March 30 - April 3, 1998 Orlando, Florida, Los Alamitos, Calif.: IEEE Computer Press , 1998, s. 226-232Konferensbidrag (Refereegranskat)
    Abstract [en]

    In array radar signal processing applications, the processing demands range from tens of GFLOPS to several TFLOPS. To address this, as well as the, size and power dissipation issues, a special purpose “array signal processing” architecture is proposed. We argue that a combined MIMD-SIMD system can give flexibility, scalability, and programmability as well as high computing density. The MIMD system level, where SIMD modules are interconnected by a fiber-optic real-time network, provides the high level flexibility while the SIMD module level provides the compute density. In this paper we evaluate different design alternatives and show how the VEGA architecture was derived. By examining the applications and the algorithms used, the SIMD mesh processor is found be sufficient. However, the smaller the meshes are the better is the flexibility and efficiency. Then, based on prototype VLSI implementations and on instruction statistics, we find that a relatively large pipelined processing element maximises the performance per area. It is thereby concluded that the small SIMD mesh processor array with powerful processing elements is the best choice. These observations are further exploited in the design of the single-chip SIMD processor array to be included in the MIMD-style overall system. The system scales from 6.4 GFLOPS to several TFLOPS peak performance.

  • 9.
    Ul-Abdin, Zain
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Åhlander, Anders
    Saab AB, Gothenburg, Sweden.
    Svensson, Bertil
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Energy-Efficient Synthetic-Aperture Radar Processing on a Manycore Architecture2013Ingår i: Proceedings: International Conference on Parallel Processing : The 42nd Annual Conference : ICPP 2013 : 1-4 October 2013 : Lyon, France / [ed] Randall Bilof, Piscataway, NJ: IEEE conference proceedings, 2013, s. 330-338, artikel-id 6687366Konferensbidrag (Refereegranskat)
    Abstract [en]

    The next generation radar systems have high performance demands on the signal processing chain. Examples include the advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in realtime. Manycore architectures are gaining attention as a means to overcome the computational requirements of the complex radar signal processing by exploiting massive parallelism inherent in the algorithms in an energy efficient manner.

    In this paper, we evaluate a manycore architecture, namely a 16-core Epiphany processor, by implementing two significantly large case studies, viz. an autofocus criterion calculation and the fast factorized back-projection algorithm, both key componentsin modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance and programmability. One of the Epiphany implementations demonstrates the usefulness of the architecture for the streaming based algorithm (the autofocus criterion calculation) by achieving a speedup of 8.9x over a sequential implementation on a state-of-the-art general-purpose processor of a later silicon technology generation and operating at a 2.7x higher clock speed. On the other case study, a highly memory-intensive algorithm (fast factorized backprojection), the Epiphany architecture shows a speedup of 4.25x. For embedded signal processing, low power dissipation is equally important as computational performance. In our case studies, the Epiphany implementations of the two algorithms are, respectively, 78x and 38x more energy efficient. © 2013 IEEE

  • 10.
    Ul-Abdin, Zain
    et al.
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Åhlander, Anders
    Saab AB, Gothenburg, Sweden.
    Svensson, Bertil
    Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Real-time Radar Signal Processing on Massively Parallel Processor Arrays2013Ingår i: Conference Record of The Forty-Seventh Asilomar Conference on Signals, Systems & Computers: November 3–6, 2013 Pacific Grove, California / [ed] Michael B. Matthews, Piscataway, NJ: IEEE Signal Processing Society, 2013, s. 1810-1814Konferensbidrag (Refereegranskat)
    Abstract [en]

    The next generation radar systems have high performance demands on the signal processing chain. Among these are advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in realtime. Massively Parallel Processor Arrays (MPPAs) are gaining attention to cope with the computational requirements of complex radar signal processing by exploiting the massive parallelism inherent in the algorithms in an energy efficient manner.

    In this paper, we evaluate two such massively parallel architectures, namely, Ambric and Epiphany, by implementing a significantly large case study of autofocus criterion calculation, which is a key component in future synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance, energy efficiency, and programmability. ©2013 IEEE.

  • 11.
    Zain-ul-Abdin,
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Åhlander, Anders
    Business Area Electronic Defence Systems, Saab AB, Gothenburg, Sweden.
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Programming Real-time Autofocus on a Massively Parallel Reconfigurable Architecture using Occam-pi2011Ingår i: Proceedings of the 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM'2011), Los Alamitos, Calif.: IEEE Computer Society, 2011, s. 194-201Konferensbidrag (Refereegranskat)
    Abstract [en]

    Recently we proposed occam-pi as a high-level language for programming massively parallel reconfigurable architectures. The design of occam-pi incorporates ideas from CSP and pi-calculus to facilitate expressing parallelism and reconfigurability. The feasability of this approach was illustratedby building three occam-pi implementations of DCT executing on an Ambric. However, because DCT is a simple and well studied algorithm it remained uncertain whether occam-pi would also be effective for programming novel, more complex algorithms.

    In this paper, we demonstrate the applicability of occam-pi for expressing various degrees of parallelism by implementinga significantly large case-study of focus criterion calculation inan autofocus algorithm on the Ambric architecture. Autofocus is a key component of synthetic aperture radar systems. Two implementations of focus criterion calculation were developedand evaluated on the basis of performance. The comparison of the performance results with a single threaded software implementation of the same algorithm show that the throughput of the two implementations are 11x and 23x higher than the sequential implementation despite a much lower (9x) clock frequency. The two designs are, respectively, 29x and 40x moreenergy efficient.

  • 12.
    Åhlander, Anders
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Efficient parallell architectures for future radar signal processing2007Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    The processing demands on future embedded radar signal processors may stretch to several trillions of floating-point operations per second (TFLOPS). This is an increase of two to three orders of magnitude realtive to the requirements of today. Still, the tight size and power constraints are unchanged. To meet this, new, highly parallel computer systems are needed. The systems should efficiently deliver very high performance as well as being general enough. Another challenge for future signal processors is the requirement for having huge working memories that are accessed in complicated patterns.

    This thesis analyses the challenges of two classes of radar signal processing applications, namely Space-Time Adaptive Processing (STAP), which represents performance-intensive applications, and Synthetic Aperture Radar (SAR) processing, which represents memory-intensive applications. In addition to the actual performance and memory aspects of the applications, the desire for low-effort application development and maintenance is taken into consideration.

    A multiple SIMD architecture is proposed for the STAP calculations. This architecture gives a combination of the high computational density in the SIMD processing modules with the overall flexibility provided on the system level. An embedded signal processing system based on the architecture is shown to be capable of TFLOPS class performance using standard CMOS VLSI technology available in the year 2001. The system is, for the given application domain, considered to have the same generality as commercial off-the-shelf (COTS) hardware, but has several years of time lead over COTS with regard to the computational performance.

    The studied SAR processing is characterized by operating on huge data sets and having varying, non-linear data access paths. For this, algorithm solutions and execution schemes in inerplay with a system parallelization approach are proposed. It is shown that it is possible to obtain efficient memory accesses, despite the omplicated memory access patterns. It is also shown that the computational burden from complex interpolation kernels can be reduced through extensive calculation reuse.

    Efficient engineering of complex applications in this context is discussed. The use of semi-transparent, platform-based development is demonstrated for STAP and SAR, and advocated for obtaining high engineering defficiency and long system sustainability, as well as high performance efficiency.

    The overall conclusion drawn from this work is that a solid knowledge of the application domain and its future requirements, in combination with an understanding of its interaction with computational architectures, potentially enables several years of lead time in the realization of new, advanced signal prodcessing products. The important requirements on programmability and sustainability must also be taken into account in order to achieve a viable signal processing solution.

  • 13.
    Åhlander, Anders
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Hellsten, H.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE).
    Lind, K.
    Saab Microwave Systems, Gothenburg, Sweden.
    Lindgren, J.
    Saab Microwave Systems, Gothenburg, Sweden.
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Architectural challenges in memory-intensive, real-time image forming2007Ingår i: International Conference on Parallel Processing, 2007. ICPP 2007 / [ed] Li Jiandong, IEEE Press, 2007, s. 35-45Konferensbidrag (Refereegranskat)
    Abstract [en]

    The real-time image forming in future, high-end synthetic aperture radar systems is an example of an application that puts new demands on computer architectures. The initial question is whether it is at all possible to meet the demands with state-of-the-art technology or foreseeable new technology. It is therefore crucial to understand the computational flow, with its associated memory, bandwidth and processing demands. In this paper we analyse the application in order to, primarily, understand the algorithms and identify the challenges they present on a basic architectural level. The processing in the radar system is characterized by working on huge data sets, having complex memory access patterns, and doing real-time compensations for flight path errors. We propose algorithm solutions and execution schemes in interplay with a two-level (coarse-grain/fine-grain) system parallelization approach, and we provide approximate models on which the demands are quantified. In particular, we consider the choice of method for the performance-intensive data interpolations. This choice presents a trade-off problem between computational performance and size of working memory. The results of this "upstream" study will serve as a basis for further, more detailed architecture studies.

  • 14.
    Åhlander, Anders
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
    Taveniku, Mikael
    Department of Computer Engineering, Chalmers University of Technology, Sweden.
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS). Department of Computer Engineering, Chalmers University of Technology, Sweden.
    A multiple SIMD approach to radar signal processing1996Ingår i: 1996 IEEE TENCON: Digital signal processing applications : proceedings : The University of Western Australia, Perth, Western Australia, 26-29 November 1996, Vol. 2 / [ed] Roberto Togneri, Piscataway, NJ: IEEE Press, 1996, s. 852-857Konferensbidrag (Övrigt vetenskapligt)
    Abstract [en]

    Next generation radar systems, with phase-controlled array antennas, will have to process data that is many times larger than in current systems. This requires an enormous computing power. Even in a relatively small airborne radar system, with hard size and power consumption constraints, a sustained computing power of 40 GOPS (or 40 GFLOPS, if floating point calculations are used) will be needed to perform only the subset of the calculations known as the space-time adaptive processing, STAP Consequently, there is a need for new parallel computing modules, as well as new overall system architectures and application development environments. In this paper, a modular architecture with highly parallel SIMD-modules is presented as a promising solution, capable of handling STAP. A version of the architecture, equipped with bit-serial floating point PEs, is described and evaluated. Implementation technology aspects are discussed.

  • 15.
    Åhlander, Anders
    et al.
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Åström, Anders
    Airborne Radar Division, Ericsson Microwave Systems AB, Mölndal, Sweden.
    Svensson, Bertil
    Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
    Taveniku, Mikael
    XCube Communication, Westford, MA, USA.
    Meeting Engineer Efficiency Requirements in Highly Parallel Signal Processing by Using Platforms2005Ingår i: Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems: November 14-16, 2005, Phoenix, AZ, USA / [ed] S. Q. Zheng, Anaheim: ACTA Press, 2005, s. 693-700Konferensbidrag (Övrig (populärvetenskap, debatt, mm))
    Abstract [en]

    One of the driving forces behind the development of new, highly parallel architectures is the need for embedded high-performance computing. The development of advanced applications on such architectures is, however, potentially connected to high costs. Cost-effective devel opment requires tools and processes that provide engineer efficiency, in this case tools and processes that help the developer master the application complexity. Related to engineer efficiency are the important concepts of system sustainability and flexibility. To address these issues, a platform approach can be taken. The platform should offer an understandable and stable development model, and at the same time give the possibility to take advantage of the rapid technology development, including the use of new parallel architectures. Thus it must support multiple hard ware targets, and the development model should decouple application development from mapping aspects. Two radar signal processing examples, one compute-intensive STAP and one data-intensive SAR, are used to illustrate the need. The GEPARD platform is presented as an example of our approach, and we argue that the described platform is a good fit for advanced signal processing development, facilitating the desired engineer efficiency, sustainability, and flexibility.

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