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  • 1.
    Jam, Reza Jafari
    et al.
    Lund Univ, Div Solid State Phys & NanoLund, Box 118, SE-21100 Lund, Sweden..
    Persson, Axel R.
    Lund Univ, Centr & Anal & Synth & NanoLund, POB 124, SE-21100 Lund, Sweden..
    Barrigon, Enrique
    Lund Univ, Div Solid State Phys & NanoLund, Box 118, SE-21100 Lund, Sweden..
    Heurlin, Magnus
    Lund Univ, Div Solid State Phys & NanoLund, Box 118, SE-21100 Lund, Sweden..
    Geijselaers, Irene
    Lund Univ, Div Solid State Phys & NanoLund, Box 118, SE-21100 Lund, Sweden..
    Gomez, Victor J.
    Lund Univ, Div Solid State Phys & NanoLund, Box 118, SE-21100 Lund, Sweden..
    Hultin, Olof
    RISE Res Inst Sweden, Scheelevagen 17, S-22370 Lund, Sweden..
    Samuelson, Lars
    Lund Univ, Div Solid State Phys & NanoLund, Box 118, SE-21100 Lund, Sweden..
    Borgstrom, Magnus T.
    Lund Univ, Div Solid State Phys & NanoLund, Box 118, SE-21100 Lund, Sweden..
    Pettersson, Håkan
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), MPE-lab. Lund Univ, Div Solid State Phys & NanoLund, Box 118, SE-21100 Lund, Sweden.;Halmstad Univ, Sch Informat Technol, Box 823, S-30118 Halmstad, Sweden..
    Template-assisted vapour-liquid-solid growth of InP nanowires on (001) InP and Si substrates2020In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 12, no 2, p. 888-894Article in journal (Refereed)
    Abstract [en]

    We report on the synthesis of vertical InP nanowire arrays on (001) InP and Si substrates using template-assisted vapour-liquid-solid growth. A thick silicon oxide layer was first deposited on the substrates. The samples were then patterned by electron beam lithography and deep dry etching through the oxide layer down to the substrate surface. Gold seed particles were subsequently deposited in the holes of the pattern by the use of pulse electrodeposition. The subsequent growth of nanowires by the vapour-liquid-solid method was guided towards the [001] direction by the patterned oxide template, and displayed a high growth yield with respect to the array of holes in the template. In order to confirm the versatility and robustness of the process, we have also demonstrated guided growth of InP nanowire p-n junctions and InP/InAs/InP nanowire heterostructures on (001) InP substrates. Our results show a promising route to monolithically integrate III-V nanowire heterostructure devices with commercially viable (001) silicon platforms.

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