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Low Power Unrolled CORDIC Architectures
Lund University, Lund, Sweden.
Lund University, Lund, Sweden.
Lund University, Lund, Sweden.
Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0003-4828-7488
2015 (English)In: 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) / [ed] Jim Tørresen, Snorre Aunet, Øyvind Kallevik Grutle, Ivan Ring Nielsen, Tor Sverre Lande, Piscataway, NJ: IEEE Press, 2015Conference paper, Oral presentation with published abstract (Refereed)
Abstract [en]

This paper shows a novel methodology to improve unrolled CORDIC architectures. The methodology is based on removing adder stages starting from the first stage. As an example, a 19-stage CORDIC is used but the methodology is applicable on CORDICs with an arbitrary number of stages. The CORDIC is implemented, simulated, and synthesized into hardware. In the paper, the performance is shown to be increased by 23% and that the dynamic power can be reduced by 27%. © 2014 IEEE

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE Press, 2015.
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:hh:diva-29718DOI: 10.1109/NORCHIP.2015.7364396ISI: 000380441400043Scopus ID: 2-s2.0-84963742027ISBN: 978-1-4673-6576-5 (print)OAI: oai:DiVA.org:hh-29718DiVA: diva2:866689
Conference
2015 NORCAS Conference, IEEE Nordic Circuits and Systems Conference, Oslo, Norway, October 26-28, 2015
Funder
VINNOVA
Note

Funding: STMicroelectronics, SSF, and Vinnova

Available from: 2015-11-03 Created: 2015-11-03 Last updated: 2017-05-15Bibliographically approved
In thesis
1. Methodologies for Approximation of Unary Functions and Their Implementation in Hardware
Open this publication in new window or tab >>Methodologies for Approximation of Unary Functions and Their Implementation in Hardware
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Applications in computer graphics, digital signal processing, communication systems, robotics, astrophysics, fluid physics and many other areas have evolved to become very computation intensive. Algorithms are becoming increasingly complex and require higher accuracy in the computations. In addition, software solutions for these applications are in many cases not sufficient in terms of performance. A hardware implementation is therefore needed. A recurring bottleneck in the algorithms is the performance of the approximations of unary functions, such as trigonometric functions, logarithms and the square root, as well as binary functions such as division. The challenge is therefore to develop a methodology for the implementation of approximations of unary functions in hardware that can cope with the growing requirements. The methodology is required to result in fast execution time, low complexity basic operations that are simple to implement in hardware, and – sincemany applications are battery powered – low power consumption. To ensure appropriate performance of the entire computation in which the approximation is a part, the characteristics and distribution of the approximation error are also things that must be possible to manage. The new approximation methodologies presented in this thesis are of the type that aims to reduce the sizes of the look-up tables by the use of auxiliary functions. They are founded on a synthesis of parabolic functions by multiplication – instead of addition, which is the most common. Three approximation methodologies have been developed; the two last being further developments of the first. For some functions, such as roots, inverse and inverse roots, a straightforward solution with an approximation is not manageable. Since these functions are frequent in many computation intensive algorithms, it is necessary to find very efficient implementations of these functions. New methods for this are also presented in this thesis. They are all founded on working in a floating-point format, and, for the roots functions, a change of number base is also used. The transformations not only enable simpler solutions but also increased accuracy, since the approximation algorithm is performed on a mantissa of limited range. Tools for error analysis have been developed as well. The characteristics and distribution of the approximation error in the new methodologies are presented and compared with existing state-of-the-art methods such as CORDIC. The verification and evaluation of the solutions have to a large extent been made as comparative ASIC implementations with other approximation methods, separately or embedded in algorithms. As an example, an implementation of the logarithm made using the third methodology developed, Harmonized Parabolic Synthesis (HPS), is compared with an implementation using the CORDIC algorithm. Both implementations are designed to provide 15-bit resolution. The design implemented using HPS performs 12 times better than the CORDIC implementation in terms of throughput. In terms of energy consumption, the new methodology consumes 96% less. The chip area is 60% smaller than for the CORDIC algorithm. In summary, the new approximation methodologies presented are found to well meet the demanding requirements that exist in this area.

Place, publisher, year, edition, pages
Halmstad: Halmstad University Press, 2016. 76 p.
Series
Halmstad University Dissertations, 21
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-30983 (URN)978-91-87045-45-5 (ISBN)978-91-87045-44-8 (ISBN)
Public defence
2016-09-02, Wigforssalen, Halmstad, 13:00 (English)
Opponent
Supervisors
Available from: 2016-06-08 Created: 2016-05-31 Last updated: 2017-05-15Bibliographically approved

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