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Energy-Efficient Synthetic-Aperture Radar Processing on a Manycore Architecture
Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0002-4932-4036
Saab AB, Gothenburg, Sweden.
Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0001-6625-6533
2013 (English)In: Proceedings: International Conference on Parallel Processing : The 42nd Annual Conference : ICPP 2013 : 1-4 October 2013 : Lyon, France / [ed] Randall Bilof, Piscataway, NJ: IEEE conference proceedings, 2013, 330-338 p., 6687366Conference paper, Published paper (Refereed)
Abstract [en]

The next generation radar systems have high performance demands on the signal processing chain. Examples include the advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in realtime. Manycore architectures are gaining attention as a means to overcome the computational requirements of the complex radar signal processing by exploiting massive parallelism inherent in the algorithms in an energy efficient manner.

In this paper, we evaluate a manycore architecture, namely a 16-core Epiphany processor, by implementing two significantly large case studies, viz. an autofocus criterion calculation and the fast factorized back-projection algorithm, both key componentsin modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance and programmability. One of the Epiphany implementations demonstrates the usefulness of the architecture for the streaming based algorithm (the autofocus criterion calculation) by achieving a speedup of 8.9x over a sequential implementation on a state-of-the-art general-purpose processor of a later silicon technology generation and operating at a 2.7x higher clock speed. On the other case study, a highly memory-intensive algorithm (fast factorized backprojection), the Epiphany architecture shows a speedup of 4.25x. For embedded signal processing, low power dissipation is equally important as computational performance. In our case studies, the Epiphany implementations of the two algorithms are, respectively, 78x and 38x more energy efficient. © 2013 IEEE

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE conference proceedings, 2013. 330-338 p., 6687366
Series
International Conference on Parallel Processing. Proceedings, ISSN 0190-3918
Keyword [en]
Manycore architecture, Parallel programming, Radar signal processing
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:hh:diva-23888DOI: 10.1109/ICPP.2013.42ISI: 000330046000033Scopus ID: 2-s2.0-84893267719ISBN: 978-0-7695-5117-3 (electronic)ISBN: 978-1-4799-1448-7 (print)OAI: oai:DiVA.org:hh-23888DiVA: diva2:660761
Conference
2013 International Conference on Parallel Processing (ICPP-2013), The 42nd Annual Conference, October 1-4, 2013, École Normale Supérieure de Lyon, Lyon, France
Available from: 2013-10-30 Created: 2013-10-30 Last updated: 2017-04-11Bibliographically approved

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Citation style
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