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Synchronizing a high-speed SIMD processor array
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
2001 (English)In: Euromicro symposium on digital systems design: architectures, methods and tools, Los Alamitos: IEEE Computer Society, 2001, 376-381 p.Conference paper, Published paper (Refereed)
Abstract [en]

A synchronization method for a high speed scalable SIMD (Single Instruction stream Multiple Data stream) processor array is presented The method is developed for an architecture using distributed clocking and hierarchical SIMD control. In such an architecture, scalability is radically enhanced by an array-size independent (local) clock skew. This paper focuses on the instruction start synchronization problem inherent in a processor array when using the SIMD mode of control and distributed clocking. It is shown how this can be solved in hardware, and bounds on the tolerable skew using this method are presented.

Place, publisher, year, edition, pages
Los Alamitos: IEEE Computer Society, 2001. 376-381 p.
Keyword [en]
distributed clocking, hierarchical SIMD control, high-speed SIMD processor array, instruction start synchronization problem, scalability, synchronization method, tolerable skew
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:hh:diva-18770DOI: 10.1109/DSD.2001.952338ISI: 000171593300053ISBN: 0-7695-1240-2 OAI: oai:DiVA.org:hh-18770DiVA: diva2:623320
Conference
Euromicro Symposium on Digital Systems Design, September 4-6, 2001, Warsaw, Poland
Available from: 2013-05-27 Created: 2012-06-25 Last updated: 2013-05-27Bibliographically approved

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Citation style
  • apa
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