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Parabolic Synthesis
Department of Electrical and Information Technology Faculty of Engineering, LTH, Lund University, Lund, Sweden.ORCID iD: 0000-0003-4828-7488
2011 (English)Licentiate thesis, monograph (Other academic)
Abstract [en]

Many consumer products, such as within the computer areas, computer graphics, digital signal processing, communication systems, robotics, navigation, astrophysics, fluid physics, etc. are searching for high computational performance as a consequence of increasingly more advanced algorithms in these applications. Until recently the down scaling of the hardware technology has been able to fulfill these higher demands from the more advanced algorithms with higher clock rates on the chips. This that the development of hardware technology performance has stagnated has moved the interest more over to implementation of algorithms in hardware. Especially within wireless communication the desire for higher transmission rates has increased the interest for algorithm implementation methodologies. The scope of this thesis is mainly on the developed methodology of parabolic synthesis. The parabolic synthesis methodology is a methodology for implementing approximations of unary functions in hardware. The methodology is described with the criteria's that have to be fulfilled to perform an approximation on a unary function. The hardware architecture of the methodology is described and to this a special hardware that performs the squaring operation. The outcome of the presented research is a novel methodology for implementing approximations of unary functions such as trigonometric functions, logarithmic functions, as well as square root and division functions etc. The architecture of the processing part automatically gives a high degree of parallelism. The methodology is founded on operations that are simple to implement in hardware such as addition, shifts, multiplication, contributes to that the implementation in hardware is simple to perform. The hardware architecture is characterized by a high degree of parallelism that gives a short critical path and fast computation. The structure of the methodology will also assure an area efficient hardware implementation.

Place, publisher, year, edition, pages
Lund: Lund University , 2011. , 69 p.
Series
Series of licentiate and doctoral theses (Department of Electrical and Information Technology, Lund University), ISSN 1654-790X ; 28
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:hh:diva-22338Libris ID: 12280184ISBN: 978-91-7473-069-2 (print)OAI: oai:DiVA.org:hh-22338DiVA: diva2:623112
Presentation
2011-01-28, Lecture hall E:2311, E-building, Ole Römers väg 3, Faculty of Engineering, Lund University, Lund, 10:15
Opponent
Supervisors
Available from: 2013-06-04 Created: 2013-05-24 Last updated: 2017-05-15Bibliographically approved

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Hertz, Erik
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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
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