Modern hardware description languages support code generation constructs like generate/endgenerate in Verilog. These constructs are used to describe regular or parameterized hardware designsand, when used effectively, can make hardware descriptions shorter, moreunderstandable, and more reusable. In practice, however, designers avoidthese abstractions because it is difficult to understand and predict theproperties of the generated code. Is the generated code even type safe?Is it synthesizable? What physical resources (e.g. combinatorial gatesand flip-flops) does it require? It is often impossible to answer thesequestions without first generating the fully-expanded code. In the Verilog and VHDL communities, this generation process is referred to as elaboration.This paper proposes a disciplined approach to elaboration in Verilog.∗1 By viewing Verilog as a statically typed two-level language, we are able to reflect the distinction between values that are known at elaborationtime and values that are part of the circuit computation. This distinctionis crucial for determining whether generative constructs, such as iterationand module parameters, are used in a synthesizable manner. This allowsus to develop a static type system that guarantees synthesizability. Thetype system achieves safety by performing additional checking on generative constructs and array indices. To illustrate this approach, we developa core calculus for Verilog that we call Featherweight Verilog (FV) andan associated static type system. We formally define a preprocessing stepanalogous to the elaboration phase of Verilog, and the kinds of errors thatcan occur during this phase. Finally, we show that a well-typed designcannot cause preprocessing errors, and that the result of its elaborationis always a synthesizable circuit.