Process algebraic verification of SystemC codes
2008 (English)In: Application of Concurrency to System Design, 2008. ACSD 2008. 8th International Conference on / [ed] Billington, J, Duan, Z, Koutny, M, New York: IEEE Press, 2008, 62-67 p.Conference paper, Published paper (Refereed)
Abstract [en]
SystemC is an IEEE standard system-level language used in hardware/software co-design and has been widely adopted in the industry. This paper describes a formal approach to verifying SystemC codes by providing a mapping to the process algebra mCRL2. The outstanding advantages of mCRL2 are the support for different data types and a powerful tool-set for model reduction and analysis. A tool is implemented to automatically perform the proposed mapping. This translation enabled us to exploit process-algebraic verification techniques to analyze a number of case-studies, including the formal analysis of a single-cycle and a pipelined MIPS processor specified in SystemC.
Place, publisher, year, edition, pages
New York: IEEE Press, 2008. 62-67 p.
Series
International Conference on Application of Concurrency to System Design. Proceedings, ISSN 1550-4808
Keyword [en]
Algebra, Computer industry, Hardware, Logic, Mathematics, Physics, Reduced order systems, Sequential circuits, Software standards, System-level design
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:hh:diva-20504DOI: 10.1109/ACSD.2008.4574597ISI: 000260161500011Scopus ID: 2-s2.0-51549092942ISBN: 978-1-4244-1838-1 ISBN: 978-1-4244-1839-8 OAI: oai:DiVA.org:hh-20504DiVA: diva2:584683
Conference
8th International Conference on Application of Concurrence System Design, Xian, PEOPLES R CHINA, JUN 23-27, 2008
2013-01-092013-01-082014-11-11Bibliographically approved