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Model checking Verilog descriptions of cell libraries
Department of Computer Science TU Eindhoven, P.O. Box 513 Eindhoven, The Netherlands.
Fenix Design Automation P.O. Box 920 Eindhoven, The Netherlands.
Department of Computer Science TU Eindhoven, P.O. Box 513 Eindhoven, The Netherlands.ORCID iD: 0000-0002-4869-6794
2009 (English)In: 2009 Ninth International Conference on Application of Concurrency to System Design: Proceedings, Los Alamitos, Calif.: IEEE Computer Society, 2009, 128-137 p.Conference paper, Published paper (Refereed)
Abstract [en]

We present a formal semantics for a subset of Verilog, commonly used to describe cell libraries, in terms of transition systems. Such transition systems can serve as input to symbolic model checking, for example equivalence checking with a transistor netlist description. We implement our formal semantics as an encoding from the subset of Verilog to the input language of the SMV model-checker. Experiments show that this approach is able to verify complete cell libraries.

Place, publisher, year, edition, pages
Los Alamitos, Calif.: IEEE Computer Society, 2009. 128-137 p.
Keyword [en]
Cell library, Equivalence checking, Formal semantics, Netlist, SMV model, Symbolic model checking, Transition system, Verilog
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:hh:diva-20509DOI: 10.1109/ACSD.2009.18ISI: 000275024600015Scopus ID: 2-s2.0-70549112299ISBN: 978-0-7695-3697-2 OAI: oai:DiVA.org:hh-20509DiVA: diva2:584680
Conference
9th International Conference on Application of Concurrency to System Design, Augsburg, GERMANY, JUL 01-03, 2009
Available from: 2013-01-09 Created: 2013-01-08 Last updated: 2014-11-11Bibliographically approved

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Mousavi, Mohammad Reza
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CiteExportLink to record
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Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
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Language
  • de-DE
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  • nn-NO
  • nn-NB
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Output format
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  • asciidoc
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