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Formal analysis of systemc designs in process algebra
Ecole Polytechnique F́ed́erale de Lausanne, Station 14, CH-1015 Lausanne, Switzerland.
Eindhoven University of Technology, P.O. Box 513, NL-5600MB, Eindhoven, Netherlands.ORCID iD: 0000-0002-4869-6794
Reykjavik University, Reykjavik, Iceland.
2011 (English)In: Fundamenta Informaticae, ISSN 0169-2968, Vol. 107, 19-42 p.Article in journal (Refereed) Published
Abstract [en]

SystemC is an IEEE standard system-level language used in hardware/software co-design and has been widely adopted in the industry. This paper describes a formal approach to verifying SystemC designs by providing a mapping to the process algebra mCRL2. Our mapping formalizes both the simulation semantics as well as exhaustive state-space exploration of SystemC designs. By exploiting the existing reduction techniques of mCRL2 and also its model-checking tools, we efficiently locate the race conditions in a system and resolve them. A tool is implemented to automatically perform the proposed mapping. This mapping and the implemented tool enabled us to exploit process-algebraic verification techniques to analyze a number of case-studies, including the formal analysis of a single-cycle and a pipelined MIPS processor specified in SystemC.

Place, publisher, year, edition, pages
Amsterdam: IOS Press, 2011. Vol. 107, 19-42 p.
Keyword [en]
Formal Verification, mCRL2, Process Algebra, SystemC
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:hh:diva-20335DOI: 10.3233/FI-2011-391ISI: 000294729300002Scopus ID: 2-s2.0-80052639615OAI: oai:DiVA.org:hh-20335DiVA: diva2:583421
Available from: 2013-01-08 Created: 2013-01-08 Last updated: 2014-11-11Bibliographically approved

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Mousavi, Mohammad Reza
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CiteExportLink to record
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Citation style
  • apa
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Language
  • de-DE
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  • nn-NB
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  • Other locale
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Output format
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  • asciidoc
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