Next generation radar systems, with phase-controlled array antennas, will have to process data that is many times larger than in current systems. This requires an enormous computing power. Even in a relatively small airborne radar system, with hard size and power consumption constraints, a sustained computing power of 40 GOPS (or 40 GFLOPS, if floating point calculations are used) will be needed to perform only the subset of the calculations known as the space-time adaptive processing, STAP Consequently, there is a need for new parallel computing modules, as well as new overall system architectures and application development environments. In this paper, a modular architecture with highly parallel SIMD-modules is presented as a promising solution, capable of handling STAP. A version of the architecture, equipped with bit-serial floating point PEs, is described and evaluated. Implementation technology aspects are discussed.