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Matrismultiplikation i FPGA
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
2003 (Swedish)Independent thesis Basic level (degree of Bachelor)Student thesis
Abstract [sv]
In modern, advanced radar applications there are high performance demands on the signal processing, which may comprise digital beamforming, doppler filtering and digital pulse compression. Much data has to be processed in a short time. Moreover, there are tight size and power constraints. In next generation radar systems, with phased array antennas, the amount of calculations are hundreds or thousands times larger than in present systems. New parallel computing architectures are needed to meet the increased performance demands. FPGA’s have attracted a lot of attention in the last few years, thanks to their improved density and speed. Since the interest for signal processing is large, FPGA manufactures have developed circuits and tools to support applications in that area. The overall goal of the project is to evaluate the size and performance figures of an FPGA realization of digital, adaptive beamforming. In the future, the results will be compared to other solutions, like microprocessor and ASIC based ones.
Place, publisher, year, edition, pages
2003.
Keyword [sv]
FPGA, QR, array processor, radar, adaptiv lobformning, matrismultiplikation
Identifiers
URN: urn:nbn:se:hh:diva-11398Local ID: U10417OAI: oai:DiVA.org:hh-11398DiVA: diva2:366529
Uppsok
Technology
Note
Denna uppsats kan beställas från arkivet / This paper can be ordered from the archive. Kontakta / Contact: arkivet@hh.seAvailable from: 2010-11-09 Created: 2010-11-09Bibliographically approved

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