Multiple FPGA-loader 2001 (Swedish)Independent thesis Basic level (degree of Bachelor)Student thesis

Abstract [sv]

The purpose of this degree project was to construct and simulate a control-logic that runs the start up phase of two FPGA-devices. A CPLD was chosen as a controller. The specification demanded one memory on the circuit where the different FPGA-programs could be packed as one file. Two programs for each FPGA have been written to simulate a saving function. A flash-memory has been used to store the programs. Statemachines have been written in VHDL to describe the logic in the CPLD. The logic has been fully verified through logic simulations and works as planned. The logic in the CPLD is built up in a way that makes it possible to use more than two FPGA-devices on the circuits in the future. There was no time to manufacture the hardware for demonstration. The report contains the description of how the problem was solved and closer information about the software and the hardware.

Place, publisher, year, edition, pages

2001.

Keywords [sv]

FPGA

Identifiers

URN: urn:nbn:se:hh:diva-9540Local ID: U4151OAI: oai:DiVA.org:hh-9540DiVA, id: diva2:364639

Uppsok

Technology

Note

Denna uppsats kan beställas från arkivet / This paper can be ordered from the archive. Kontakta / Contact: arkivet@hh.seAvailable from: 2010-11-09 Created: 2010-11-09Bibliographically approved

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School of Information Science, Computer and Electrical Engineering (IDE)

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