Implementation av flyttalsaritmetik i FPGA 1999 (Swedish)Independent thesis Basic level (degree of Bachelor)Student thesis

Abstract [sv]

Todays new FPGAs are larger, faster and more efficient then past generations. FPGA is nowadays a suitable choice for construction implementation, instead of full custom design ASICs. It is relevant to see what FPGA can do with DSP (Digital Signal Processing). Binary fixed point arithmetic have until this stage, been the most common numeric presentation in DSP. Floating point presentation have lately been more used, why there are no facts showing how good performance the FPGA, can calculate floating point arithmetic. Furthermore it is objective to see how large the floating point implementation will be compared to fixed point arithmetic. The purpose of the project is to examine area and speed for applications with both fixed point and floating point arithmetic, implemented in Xilinx FPGAs. The fundamental arithmetic functions are addition, subtraction and multiplication. This report shows a comparison between fixed point and floating point arithmetic, implemented in Xilinx XC40150XV. The binary floating point presentation is 32 bits according to IEEE 754 standard.

Place, publisher, year, edition, pages

1999.

Keywords [sv]

FPGA, Xilinx, XC40150XV, Construction, IEEE 754, Implementation, DSP, Signal, Floating, Fix, Point, Area, Speed, Addition, Subtraction, Multiplication

Identifiers

URN: urn:nbn:se:hh:diva-8258Local ID: U2212OAI: oai:DiVA.org:hh-8258DiVA, id: diva2:363343

Uppsok

Technology

Note

Denna uppsats kan beställas från arkivet / This paper can be ordered from the archive. Kontakta / Contact: arkivet@hh.seAvailable from: 2010-11-09 Created: 2010-11-09Bibliographically approved

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School of Business and Engineering (SET)

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