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Digital Coherent Limiter
Halmstad University, School of Business and Engineering (SET).
Halmstad University, School of Business and Engineering (SET).
1999 (Swedish)Independent thesis Basic level (degree of Bachelor)Student thesis
Abstract [sv]
This Bachelor of Science thesis project has the assignment to construct a digital coherent limiter. The limiter is to be used in the receiver of a Doppler radar. It should limit the received signal to a desired boundary, an inner roof. The important function is to keep the signal phase undistorted. The reason for constructing this limiter is to give the following signal processes a margin, so they won't corrupt the signal. The limiter is to be realised in a Xilinx FPGA.
Place, publisher, year, edition, pages
1999.
Keywords [sv]
Radar digital coherent limiter FPGA Xilinx
Identifiers
URN: urn:nbn:se:hh:diva-8249Local ID: U2203OAI: oai:DiVA.org:hh-8249DiVA, id: diva2:363334
Uppsok
Technology
Note
Denna uppsats kan beställas från arkivet / This paper can be ordered from the archive. Kontakta / Contact: arkivet@hh.seAvailable from: 2010-11-09 Created: 2010-11-09Bibliographically approved

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