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The VEGA moderately parallel MIMD, moderately parallel SIMD, architecture for high performance array signal processing
Department of Computer Engineering, Chalmers University of Technology S-412 96 Goteborg, Sweden - Ericsson Microwave Systems AB, S-431 84 Molndal, Sweden .
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).ORCID iD: 0000-0002-6526-3931
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).ORCID iD: 0000-0001-6625-6533
1998 (English)In: Proceedings of the first merged International Parallel Processing Symposium & Symposium on Parallel and Distributed Processing: March 30 - April 3, 1998 Orlando, Florida, Los Alamitos, Calif.: IEEE Computer Press , 1998, 226-232 p.Conference paper, (Refereed)
Abstract [en]

In array radar signal processing applications, the processing demands range from tens of GFLOPS to several TFLOPS. To address this, as well as the, size and power dissipation issues, a special purpose “array signal processing” architecture is proposed. We argue that a combined MIMD-SIMD system can give flexibility, scalability, and programmability as well as high computing density. The MIMD system level, where SIMD modules are interconnected by a fiber-optic real-time network, provides the high level flexibility while the SIMD module level provides the compute density. In this paper we evaluate different design alternatives and show how the VEGA architecture was derived. By examining the applications and the algorithms used, the SIMD mesh processor is found be sufficient. However, the smaller the meshes are the better is the flexibility and efficiency. Then, based on prototype VLSI implementations and on instruction statistics, we find that a relatively large pipelined processing element maximises the performance per area. It is thereby concluded that the small SIMD mesh processor array with powerful processing elements is the best choice. These observations are further exploited in the design of the single-chip SIMD processor array to be included in the MIMD-style overall system. The system scales from 6.4 GFLOPS to several TFLOPS peak performance.

Place, publisher, year, edition, pages
Los Alamitos, Calif.: IEEE Computer Press , 1998. 226-232 p.
Series
International Parallel Processing Symposium & Symposium on Parallel and Distributed Processing, ISSN 1063-7133 ; 1998
Keyword [en]
VEGA, array radar signal processing, array signal processing, combined MIMD-SIMD system, parallel architecture, peak performance, pipelined processing element
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:hh:diva-2748DOI: 10.1109/IPPS.1998.669915ISI: 000073316800034Scopus ID: 2-s2.0-0031678559Local ID: 2082/3150OAI: oai:DiVA.org:hh-2748DiVA: diva2:239966
Conference
first merged International Parallel Processing Symposium & Symposium on Parallel and Distributed Processing, March 30 - April 3, 1998 Orlando, Florida
Note

©1998 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2009-08-12 Created: 2009-08-12 Last updated: 2017-02-08Bibliographically approved

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CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
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Language
  • de-DE
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Output format
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