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Algorithm for the choice of topology in reconfigurable on-chip networks with real-time support
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0001-7730-094X
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Embedded Systems (CERES).ORCID iD: 0000-0002-6526-3931
2007 (English)In: Proceedings of the 2nd international conference on Nano-Networks, Bryssels: ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering) , 2007, 1-7 p.Conference paper, (Refereed)
Abstract [en]

Many future embedded systems are likely to contain System-on-Chip solutions with on-chip networks and in order to achieve high aggregated throughputs in these networks, a switched topology can be used. For further performance improvements, the topology can be adapted to application demands, either when designing the chip or by run-time reconfiguration between different predefined application modes. In this paper, we present an algorithm for the choice of topology in, e.g., on-chip networks, considering realtime demands in terms of throughput and delay often put on such systems. To further address possible real-time demands, we include a feasibility analysis to check that the application, when mapped onto the system, will behave in line with its real-time demands. With input information about traffic characteristics, our algorithm creates a topology and generates routing information for all logical traffic channels. In a case study, we show that our algorithm results in a topology that can outperform the use of state of the art topologies for high-performance computer architectures.

Place, publisher, year, edition, pages
Bryssels: ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering) , 2007. 1-7 p.
Keyword [en]
Network-on-Chip, topology design, feasibility analysis, real-time communication, reconfigurable systems
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:hh:diva-2225Local ID: 2082/2623ISBN: 978-963-9799-10-3 (print)OAI: oai:DiVA.org:hh-2225DiVA: diva2:239443
Conference
Nanonet07 Second International Conference on Nano-NetworksCatania, Italy, September 24 - 26, 2007
Available from: 2010-09-27 Created: 2009-01-27 Last updated: 2017-05-15Bibliographically approved

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CiteExportLink to record
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
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  • Other locale
More languages
Output format
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  • text
  • asciidoc
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