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A configurable framework for stream programming exploration in baseband applications
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0001-6625-6533
2006 (English)In: 2006 IEEE International Parallel & Distributed Processing Symposium: Rhodes Island, Greece : 25-29 April, 2006, Piscataway, N.J.: IEEE Press, 2006, 8- p.Conference paper, (Refereed)
Abstract [en]

This paper presents a configurable framework to be used for rapid prototyping of stream based languages. The framework is based on a set of design patterns defining the elementary structure of a domain specific language for high-performance signal processing. A stream language prototype for baseband processing has been implemented using the framework. We introduce language constructs to efficiently handle dynamic reconfiguration of distributed processing parameters. It is also demonstrated how new language specific primitive data types and operators can be used to efficiently and machine independently express computations on bitfields and data-parallel vectors. These types and operators yield code that is readable, compact and amenable to a stricter type checking than is common practice. They make it possible for a programmer to explicitly express parallelism to be exploited by a compiler. In short, they provide a programming style that is less error prone and has the potential to lead to more efficient implementations.

Place, publisher, year, edition, pages
Piscataway, N.J.: IEEE Press, 2006. 8- p.
Keyword [en]
distributed processing, program compilers, software prototyping, telecommunication, computing, telecommunication signalling
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:hh:diva-2104DOI: 10.1109/IPDPS.2006.1639502Scopus ID: 2-s2.0-33847132885Local ID: 2082/2499ISBN: 1-4244-0054-6 OAI: oai:DiVA.org:hh-2104DiVA: diva2:239322
Conference
20th International Parallel and Distributed Processing Symposium, IPDPS 2006, Rhodes Island, Greece : 25-29 April, 2006
Note

©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2008-11-04 Created: 2008-11-04 Last updated: 2014-08-21Bibliographically approved
In thesis
1. Models and Methods for Development of DSP Applications on Manycore Processors
Open this publication in new window or tab >>Models and Methods for Development of DSP Applications on Manycore Processors
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Advanced digital signal processing systems require specialized high-performance embedded computer architectures. The term high-performance translates to large amounts of data and computations per time unit. The term embedded further implies requirements on physical size and power efficiency. Thus the requirements are of both functional and non-functional nature. This thesis addresses the development of high-performance digital signal processing systems relying on manycore technology. We propose building two-level hierarchical computer architectures for this domain of applications. Further, we outline a tool flow based on methods and analysis techniques for automated, multi-objective mapping of such applications on distributed memory manycore processors. In particular, the focus is put on how to provide a means for tunable strategies for mapping of task graphs on array structured distributed memory manycores, with respect to given application constraints. We argue for code mapping strategies based on predicted execution performance, which can be used in an auto-tuning feedback loop or to guide manual tuning directed by the programmer. Automated parallelization, optimisation and mapping to a manycore processor benefits from the use of a concurrent programming model as the starting point. Such a model allows the programmer to express different types and granularities of parallelism as well as computation characteristics of importance in the addressed class of applications. The programming model should also abstract away machine dependent hardware details. The analytical study of WCDMA baseband processing in radio base stations, presented in this thesis, suggests dataflow models as a good match to the characteristics of the application and as execution model abstracting computations on a manycore. Construction of portable tools further requires a manycore machine model and an intermediate representation. The models are needed in order to decouple algorithms, used to transform and map application software, from hardware. We propose a manycore machine model that captures common hardware resources, as well as resource dependent performance metrics for parallel computation and communication. Further, we have developed a multifunctional intermediate representation, which can be used as source for code generation and for dynamic execution analysis. Finally, we demonstrate how we can dynamically analyse execution using abstract interpretation on the intermediate representation. It is shown that the performance predictions can be used to accurately rank different mappings by best throughput or shortest end-to-end computation latency.

Place, publisher, year, edition, pages
Göteborg: Chalmers University of Technology, 2009. 173 p.
Series
Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie, ISSN 0346-718X ; 2969
Keyword
parallel processing, manycore processors, high-performance digital signal processing, dataflow, concurrent models of computation, parallel code mapping, parallel machine model, dynamic performance analysis
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-14706 (URN)978-91-7385-288-3 (ISBN)
Public defence
2009-06-10, Wigforssalen, house Visionen, Halmstad University, Kristian IV:s väg 3, Halmstad, 13:15 (English)
Opponent
Supervisors
Available from: 2011-04-20 Created: 2011-04-04 Last updated: 2011-04-20Bibliographically approved

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