hh.sePublications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Reducing Delay and Jitter in Software Control Systems
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
Real-Time Systems Laboratory Scuola Superiore Sant’Anna Pisa, Italy.
2007 (English)In: Proceedings of the 15th International Conference on Real-Time and Network Systems: RTNS’07, Vandoeuvre: Institut National Polytechnique de Lorraine , 2007, 173-182 p.Conference paper, Published paper (Refereed)
Abstract [en]

Software control systems may be subject to high interference caused by concurrency and resource sharing. Reducing delay and jitter in such systems is crucial for guaranteeing high performance and predictability. In this paper, we present a general approach for reducing delay and jitter by acting on task relative deadlines. The method allows the user to specify a deadline reduction factor for each task to better exploit the available slack according to specific jitter sensitivity. Experimental results confirm the effectiveness and the generality of the proposed approach with respect to other methods available in the literature.

Place, publisher, year, edition, pages
Vandoeuvre: Institut National Polytechnique de Lorraine , 2007. 173-182 p.
Keyword [en]
Software Control Systems, Reducing jitter, Reducing delay
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:hh:diva-1965Local ID: 2082/2360ISBN: 2-905267-53-4 ISBN: 9782905267535 OAI: oai:DiVA.org:hh-1965DiVA: diva2:239183
Conference
15th Conference on real-time and networks systems, LORIA, Nancy, France 29-30 March 2007
Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2016-03-31Bibliographically approved
In thesis
1. Enhancing the Performance of Distributed Real-time Systems
Open this publication in new window or tab >>Enhancing the Performance of Distributed Real-time Systems
2007 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Advanced embedded systems can consist of many sensors, actuators and processors that are deployed on one or several boards, while having a demand of interacting with each other and sharing resources. Communication between different components usually has strict timing constraints. There is thus a strong need to provide solutions for time critical communication. This thesis focuses on both the support of real-time services over standard switched Ethernet networks and the improvement of systems' real-time characteristics, such as reducing delay and jitter in processors and on communication links.

Switched Ethernet has been chosen in this work because of its major advantages in industry; it supports higher bit-rates than most other current LAN (Local Area Network) technologies, including field buses, still at a low cost. We propose using a star network topology with a single Ethernet switch. Each node is connected to a separate port of the switch via a full-duplex link, thereby eliminating collisions. A solid real-time communication protocol for switched Ethernet networks is proposed in the thesis, including a real-time layer between the Ethernet layer and the TCP/IP suite. The network has the capability of supporting both real-time and non real-time traffic and assuring adaptation to the surrounding protocol standards.

Most embedded systems work in a dynamic environment, where the precise behavior of the network traffic can usually not be predicted. To support real-time services, we have chosen the Earliest Deadline scheduling algorithm (EDF) because of its optimality, high efficiency and suitability for being used in adaptive schemes. To be able to increase the amount of guaranteed real-time traffic, the notion of Asymmetric Deadline Partitioning Scheme (ADPS) is introduced. ADPS allows distribution of the end-to-end deadline of a message, sent from any source node in the network to any destination node via the switch, into two sub-deadlines, one for each hop according to the load of the physical link that it must traverse.

For the EDF scheduling algorithm, the feasibility test is one of the most important techniques that provides us with information about whether or not the real-time traffic can be guaranteed by the network. With the same computational complexity as the feasibility test, a method has been developed to compute the minimum EDF-feasible deadline for a real-time task. The importance of this method in real-time applications lies in that it can be effectively used to reduce the response times of specific control activities or limit their input-output jitter. To allow more flexibility in the control of delay and jitter in real-time systems, a general approach for reducing task deadlines according to the requirements of individual tasks has been developed. The method allows the user to specify a deadline reduction factor for each task in order to better exploit the available slack according to the tasks' actual requirements.

Place, publisher, year, edition, pages
Göteborg: Chalmers university of technology, 2007. 156 p.
Series
Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie, ISSN 0346-718X ; 2599
Keyword
Switched Ethernet, Real-Time Communication, EDF scheduling, Reducation of delay and jitter
National Category
Computer Science
Identifiers
urn:nbn:se:hh:diva-1986 (URN)2082/2381 (Local ID)978-91-7291-918-1 (ISBN)2082/2381 (Archive number)2082/2381 (OAI)
Public defence
2007-05-14, Wigforssalen, Halmstad, 10:15 (English)
Opponent
Supervisors
Note

Ingår även i serien: Technical report. D / Department of Computer Science and Engineering, Chalmers University of Technology, 1653-1787 ; 28

Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2016-03-31Bibliographically approved

Open Access in DiVA

fulltext(539 kB)118 downloads
File information
File name FULLTEXT01.pdfFile size 539 kBChecksum MD5
99b6d13b3cb46ef840ef6d2e6d07110dcffda7d273c7477edbe04b3ba1cdee89c1eba5adb9a34626db1b45413420f5004cc9b6b694e97ac2b88d932ba72ccc1fa3f0e5bd3d281d8561cb37ab8036a51e
Type fulltextMimetype application/pdf

Search in DiVA

By author/editor
Hoang, Hoai
By organisation
Centre for Research on Embedded Systems (CERES)
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar
Total: 118 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Total: 108 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf