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Analyzing the Advantages of Run-Time Reconfiguration in Radar Signal Processing
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0001-6625-6533
2005 (English)In: Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems / [ed] S. Q. Zheng, Anaheim: ACTA Press, 2005, p. 701-706Conference paper, Published paper (Refereed)
Abstract [en]

Configurable architectures have emerged as one of the most powerful programmable signal processing platforms commercially available, obtaining their performance through the use of spatial parallelism. By changing the functionality of these devices during run-time, flexible mapping of signal processing applications can be made. The run-time flexibility puts requirements on the reconfiguration time that depend both on the application and on the mapping strategy. In this paper we analyze one such application, Space Time Adaptive Processing for radar signal processing, and show three different mappings and their requirements. The allowed time for run-time reconfiguration in these three cases varies from 1 ms down to 1 µs. Each has its own advantages, such as data reuse and optimization of computational kernels. Architectures with reconfiguration times in the order of 10 µs provide the flexibility needed for mapping the example in an efficient way, allowing for on-chip data reuse between the different processing stages.

Place, publisher, year, edition, pages
Anaheim: ACTA Press, 2005. p. 701-706
Keywords [en]
Reconfigurable architecture, Radar signal processing, Configuration time
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:hh:diva-413Local ID: 2082/751ISBN: 0-88986-525-6 ISBN: 9780889865259 OAI: oai:DiVA.org:hh-413DiVA, id: diva2:237592
Conference
17th IASTED International Conference on Parallel and Distributed Computing Systems, PDCS 2005, November 14-16, 2005, Phoenix, AZ, USA
Available from: 2007-01-23 Created: 2007-01-23 Last updated: 2018-03-23Bibliographically approved

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Johnsson, DennisÅhlander, AndersSvensson, Bertil

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
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Language
  • de-DE
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  • en-US
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  • nn-NO
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  • Other locale
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Output format
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  • asciidoc
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