hh.sePublications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
The REMAP Reconfigurable Architecture: a Retrospective
Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Chalmers University of Technology, Gothenburg, Sweden.
Chalmers University of Technology, Gothenburg, Sweden.
Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS). Telecommunications Research Center Vienna (FTW), Vienna, Austria.ORCID iD: 0000-0002-0562-2082
Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0001-6625-6533
Show others and affiliations
2006 (English)In: FPGA Implementations of Neural Networks, New York: Springer-Verlag New York, 2006, p. 325-360Chapter in book (Refereed)
Abstract [en]

The goal of the REMAP project was to gain new knowledge about the design and use of massively parallel computer architectures in embedded real-time systems. In order to support adaptive and learning behavior in such systems, the efficient execution of Artificial Neural Network (ANN) algorithms on regular processor arrays was in focus. The REMAP-β parallel computer built in the project was designed with ANN computations as the main target application area. This chapter gives an overview of the computational requirements found in ANN algorithms in general and motivates the use of regular processor arrays for the efficient execution of such algorithms. REMAP-β was implemented using the FPGA circuits that were available around 1990. The architecture, following the SIMD principle (Single Instruction stream, Multiple Data streams), is described, as well as the mapping of some important and representative ANN algorithms. Implemented in FPGA, the system served as an architecture laboratory. Variations of the architecture are discussed, as well as scalability of fully synchronous SIMD architectures. The design principles of a VLSI-implemented successor of REMAP-β are described, and the paper is concluded with a discussion of how the more powerful FPGA circuits of today could be used in a similar architecture. © 2006 Springer.

Place, publisher, year, edition, pages
New York: Springer-Verlag New York, 2006. p. 325-360
Keywords [en]
Artificial neural networks, parallel architecture, SIMD, field-programmable gate arrays (FPGA)
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:hh:diva-377DOI: 10.1007/0-387-28487-7_12Scopus ID: 2-s2.0-84889954052Local ID: 2082/701ISBN: 0-387-28485-0 (print)OAI: oai:DiVA.org:hh-377DiVA, id: diva2:237556
Available from: 2007-01-10 Created: 2007-01-10 Last updated: 2018-03-23Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Authority records BETA

Bengtsson, LarsNordström, TomasSvensson, Bertil

Search in DiVA

By author/editor
Bengtsson, LarsNordström, TomasSvensson, Bertil
By organisation
Halmstad Embedded and Intelligent Systems Research (EIS)Centre for Research on Embedded Systems (CERES)
Computer Sciences

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 240 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf