The REMAP project addresses questions related to the use of massively parallel, distributed computing in embedded systems. Of specific interest is the execution of artificial neural network algorithms on multiple, cooperating processor arrays. This paper concentrates on the recently finished, and currently used, processor array prototype, REMAP-β, of SIMD (Single Instruction stream, Multiple Data streams) type. The architecture and implementation of the computer is described, both its overall structure and its constituent parts. Following this comes a discussion of its use as an architecture laboratory, which stems from the fact that it is implemented using FPGA (Field Programmable Gate Array) circuits. As an architecture laboratory the prototype can be used to implement and evaluate, e.g., various Processing Element (PE) designs. A couple of examples of PE architectures, including one with floating-point support, are given. The mapping of important neural network algorithms on processor arrays of this kind is shown, and possible tuning of the architecture to meet specific processing demands is discussed. Performance figures are given as well as implications for future VLSI implementations of the array.