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A security-aware hardware scheduler for modern multi-core systems with hard real-time constraints
Iran University Of Science And Technology, Tehran, Iran.
Iran University Of Science And Technology, Tehran, Iran.
Lcis, Valence, France.
Halmstad University, School of Information Technology.ORCID iD: 0000-0002-2874-6256
2022 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 95, article id 104716Article in journal (Refereed) Published
Abstract [en]

In this paper, we propose an online security-aware hardware scheduler, the so-called Secure And Fast hardware Scheduler (SAFAS), for real-time task scheduling in multi-core systems in the presence of schedule-based side-channel attacks. To avoid such attacks and ensure that all tasks meet their deadlines, SAFAS schedules critical tasks and their replicas using a hardware-based strict Least Slack Time first (LST) algorithm independently while it independently schedules the non-critical tasks using a hardware-based EDF algorithm. SAFAS enhances the system performance and reduces the chance of side-channel attacks due to the different processing cores allocated to each task in each scheduling interval. The hardware scheduler operates independently and in parallel with the multi-core system and hides the scheduling characteristics from adversaries. The software-based Earliest Deadline First (EDF) algorithm is also used for schedulability tests and feasibility analysis of hard real-time periodic tasks to maximize the number of tasks scheduled successfully in the multi-core system. SAFAS has been synthesized and simulated on a Xilinx Vivado 2018.2 and implemented on a Spartan-7 FPGA chip. Our experimental results indicate that SAFAS increases the performance of the system by 4.8 times as compared to previous state-of-the-art hardware schedulers while guaranteeing that all critical tasks and their replicas meet their deadlines. © 2022 Elsevier B.V.

Place, publisher, year, edition, pages
Amsterdam: Elsevier, 2022. Vol. 95, article id 104716
Keywords [en]
FPGA, Hardware accelerator, Hardware sorter, High performance, Parallel sorting, Resource Efficient, Sorting network
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:hh:diva-48782DOI: 10.1016/j.micpro.2022.104716ISI: 000891761000002Scopus ID: 2-s2.0-85142136429OAI: oai:DiVA.org:hh-48782DiVA, id: diva2:1717408
Available from: 2022-12-08 Created: 2022-12-08 Last updated: 2023-08-21Bibliographically approved

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Fazeli, Mahdi

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