hh.sePublications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
ReCPE: A PE for Reconfigurable Lightweight Cryptography
George Washington University, Washington, D.C., USA.
Halmstad University, School of Information Technology.ORCID iD: 0000-0001-8806-8146
George Washington University, Washington, D.C., USA.
2021 (English)In: Proceedings: IEEE International SOC Conference, SOCC 2021 / [ed] Gang Qu; Jinjun Xiong; Danella Zhao; Venki Muthukumar; Md Farhadur Reza; Ramalingam Sridhar, Piscataway: Institute of Electrical and Electronics Engineers (IEEE), 2021, p. 176-181Conference paper, Published paper (Refereed)
Abstract [en]

The Internet-of-Things has given rise to an over-whelming number of resource-constrained devices which must communicate securely with a core server. Due to the variability in processing power among these devices, one lightweight crypto-graphic (LWC) algorithm cannot be standardized. This creates a problem for fog and cloud architectures, where a central server, is subsequently required to support many ciphers. Compounding this problem, LWC ciphers tend to require large numbers of rounds to achieve high security levels, thus occupying the server for unacceptable lengths of time. To minimize LWC overhead, we propose a novel parallel mapping of LWC ciphers and ReCPE, a reconfigurable, lightweight processing element (PE) for use in hardware security modules (HSM) and array processors such as smartNICs. The proposed design was synthesized for both FPGA and ASIC implementations. We validate the ReCPE architecture by comparing it with a baseline array processor and custom field programmable gate array (FPGA) LWC accelerators that use dynamic reconfiguration. The ReCPE architecture is shown to accelerate cryptographic processing by 2× when compared to a baseline PE, with 30% and 60% increases in logic and registers, respectively. Furthermore, we achieve a 50× improvement in dynamic reconfiguration environments when compared to custom FPGA accelerators. ©2021 IEEE

Place, publisher, year, edition, pages
Piscataway: Institute of Electrical and Electronics Engineers (IEEE), 2021. p. 176-181
Series
IEEE Proceedings, ISSN 2164-1706
Keywords [en]
Reconfigurable Architectures, Domain-Specific accelerators, Parallel machines, Cryptography
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:hh:diva-46535DOI: 10.1109/SOCC52499.2021.9739359ISI: 000814696000033Scopus ID: 2-s2.0-85127759551ISBN: 978-1-6654-2931-3 (print)OAI: oai:DiVA.org:hh-46535DiVA, id: diva2:1647821
Conference
2021 IEEE 34th International System-on-Chip Conference (SOCC), Virtual, USA, September 14-17, 2021
Available from: 2022-03-28 Created: 2022-03-28 Last updated: 2023-10-05Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Authority records

Alkabani, Yousra

Search in DiVA

By author/editor
Alkabani, Yousra
By organisation
School of Information Technology
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 92 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf