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The Harmonized Parabolic Synthesis Methodology for Hardware Efficient Function Generation with Full Error Control
Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0003-4828-7488
Lund University, Lund, Sweden.
Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0001-6625-6533
Lund University, Lund, Sweden.
2017 (English)In: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115Article in journal (Refereed) Epub ahead of print
Abstract [en]

The Harmonized Parabolic Synthesis methodology is a further development of the Parabolic Synthesis methodology for approximation of unary functions such as trigonometric functions, logarithms and the square root with moderate accuracy for ASIC implementation. These functions are extensively used in computer graphics, communication systems and many other application areas. For these high-speed applications, software solutions are in many cases not sufficient and a hardware implementation is therefore needed. The Harmonized Parabolic Synthesis methodology has two outstanding advantages: it is parallel, thus reducing the execution time, and it is based on low complexity operations, thus is simple to implement in hardware. A difference compared to other approximation methodologies is that it is a multiplicative and not additive, methodology. Compared to the Parabolic Synthesis methodologies it is possible to significantly enhance the performance in terms of reducing chip area, computation delay and power consumption. Furthermore it increases the possibility to tailor the characteristics of the error, improving conditions for subsequent calculations and the performance in design terms. To evaluate the proposed methodology, the fractional part of the logarithm has been implemented and its performance is compared to the Parabolic Synthesis methodology. The comparison is made with 15-bit resolution. The design implemented using the proposed methodology performs 3x better than the Parabolic Synthesis implementation in terms of throughput. In terms of energy consumption, the new methodology consumes 90% less. The chip area is 70% smaller than for the Parabolic Synthesis methodology. In summary, the new technology further increases the advantages of Parabolic Synthesis. © 2017 The Author(s)

Place, publisher, year, edition, pages
New York, NY: Springer, 2017.
Keyword [en]
Approximation, parabolic synthesis, unary functions, elementary functions, second-degree interpolation, arithmetic computation, look-up table, VLSI
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:hh:diva-32480DOI: 10.1007/s11265-017-1300-4Scopus ID: 2-s2.0-85032329367OAI: oai:DiVA.org:hh-32480DiVA: diva2:1049489
Available from: 2016-11-24 Created: 2016-11-24 Last updated: 2017-12-05Bibliographically approved

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Hertz, ErikSvensson, Bertil

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