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Combining the Parabolic Synthesis Methodology with Second-Degree Interpolation
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).ORCID-id: 0000-0003-4828-7488
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).ORCID-id: 0000-0001-6625-6533
Department of Electrical and Information Technology, Lund University, Lund, Sweden.
2016 (engelsk)Inngår i: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 42, s. 142-155Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

The Parabolic Synthesis methodology is an approximation methodology for implementing unary functions, such as trigonometric functions, logarithms and square root, as well as binary functions, such as division, in hardware. Unary functions are extensively used in baseband for wireless/wireline communication, computer graphics, digital signal processing, robotics, astrophysics, fluid physics, games and many other areas. For high-speed applications as well as in low-power systems, software solutions are not sufficient and a hardware implementation is therefore needed. The Parabolic Synthesis methodology is a way to implement functions in hardware based on low complexity operations that are simple to implement in hardware. A difference in the Parabolic Synthesis methodology compared to many other approximation methodologies is that it is a multiplicative, in contrast to additive, methodology. To further improve the performance of Parabolic Synthesis based designs, the methodology is combined with Second-Degree Interpolation. The paper shows that the methodology provides a significant reduction in chip area, computation delay and power consumption with preserved characteristics of the error. To evaluate this, the logarithmic function was implemented, as an example, using the Parabolic Synthesis methodology in comparison to the Parabolic Synthesis methodology combined with Second-Degree Interpolation. To further demonstrate the feasibility of both methodologies, they have been compared with the CORDIC methodology. The comparison is made on the implementation of the fractional part of the logarithmic function with a 15-bit resolution. The designs implemented using the Parabolic Synthesis methodology – with and without the Second-Degree Interpolation – perform 4x and 8x better, respectively, than the CORDIC implementation in terms of throughput. In terms of energy consumption, the CORDIC implementation consumes 140% and 800% more energy, respectively. The chip area is also smaller in the case when the Parabolic Synthesis methodology combined with Second-Degree Interpolation is used. © 2016 Elsevier B.V. All rights reserved.

sted, utgiver, år, opplag, sider
Amsterdam: Elsevier, 2016. Vol. 42, s. 142-155
Emneord [en]
Approximation, parabolic synthesis, unary functions, elementary functions, second-degree interpolation, arithmetic computation, CORDIC, VLSI, look-up table
HSV kategori
Identifikatorer
URN: urn:nbn:se:hh:diva-30500DOI: 10.1016/j.micpro.2016.01.015ISI: 000375336900011Scopus ID: 2-s2.0-84960834630OAI: oai:DiVA.org:hh-30500DiVA, id: diva2:910966
Tilgjengelig fra: 2016-03-10 Laget: 2016-03-10 Sist oppdatert: 2018-03-22bibliografisk kontrollert
Inngår i avhandling
1. Methodologies for Approximation of Unary Functions and Their Implementation in Hardware
Åpne denne publikasjonen i ny fane eller vindu >>Methodologies for Approximation of Unary Functions and Their Implementation in Hardware
2016 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

Applications in computer graphics, digital signal processing, communication systems, robotics, astrophysics, fluid physics and many other areas have evolved to become very computation intensive. Algorithms are becoming increasingly complex and require higher accuracy in the computations. In addition, software solutions for these applications are in many cases not sufficient in terms of performance. A hardware implementation is therefore needed. A recurring bottleneck in the algorithms is the performance of the approximations of unary functions, such as trigonometric functions, logarithms and the square root, as well as binary functions such as division. The challenge is therefore to develop a methodology for the implementation of approximations of unary functions in hardware that can cope with the growing requirements. The methodology is required to result in fast execution time, low complexity basic operations that are simple to implement in hardware, and – sincemany applications are battery powered – low power consumption. To ensure appropriate performance of the entire computation in which the approximation is a part, the characteristics and distribution of the approximation error are also things that must be possible to manage. The new approximation methodologies presented in this thesis are of the type that aims to reduce the sizes of the look-up tables by the use of auxiliary functions. They are founded on a synthesis of parabolic functions by multiplication – instead of addition, which is the most common. Three approximation methodologies have been developed; the two last being further developments of the first. For some functions, such as roots, inverse and inverse roots, a straightforward solution with an approximation is not manageable. Since these functions are frequent in many computation intensive algorithms, it is necessary to find very efficient implementations of these functions. New methods for this are also presented in this thesis. They are all founded on working in a floating-point format, and, for the roots functions, a change of number base is also used. The transformations not only enable simpler solutions but also increased accuracy, since the approximation algorithm is performed on a mantissa of limited range. Tools for error analysis have been developed as well. The characteristics and distribution of the approximation error in the new methodologies are presented and compared with existing state-of-the-art methods such as CORDIC. The verification and evaluation of the solutions have to a large extent been made as comparative ASIC implementations with other approximation methods, separately or embedded in algorithms. As an example, an implementation of the logarithm made using the third methodology developed, Harmonized Parabolic Synthesis (HPS), is compared with an implementation using the CORDIC algorithm. Both implementations are designed to provide 15-bit resolution. The design implemented using HPS performs 12 times better than the CORDIC implementation in terms of throughput. In terms of energy consumption, the new methodology consumes 96% less. The chip area is 60% smaller than for the CORDIC algorithm. In summary, the new approximation methodologies presented are found to well meet the demanding requirements that exist in this area.

sted, utgiver, år, opplag, sider
Halmstad: Halmstad University Press, 2016. s. 76
Serie
Halmstad University Dissertations ; 21
HSV kategori
Identifikatorer
urn:nbn:se:hh:diva-30983 (URN)978-91-87045-45-5 (ISBN)978-91-87045-44-8 (ISBN)
Disputas
2016-09-02, Wigforssalen, Halmstad, 13:00 (engelsk)
Opponent
Veileder
Tilgjengelig fra: 2016-06-08 Laget: 2016-05-31 Sist oppdatert: 2018-03-22bibliografisk kontrollert

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