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Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability
Rice University, Houston, TX.
Rice University, Houston, TX.
Rice University, Houston, TX.
Rice University, Houston, TX.
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2008 (Engelska)Ingår i: PEPM '08: proceedings of the 2008 ACM SIGPLAN Symposium on Partial Evaluation and Semantics-Based Program Manipulation, San Francisco, California, USA, January 7-8, 2008, New York, NY, USA: ACM Press, 2008, s. 13-20Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog. These constructs are intended to describe regular or parameterized hardware designs and, when used effectively, can make hardware descriptions shorter, more understandable, and more reusable. In practice, however, designers avoid these constructs because it is difficult to understand and predict the properties of the generated code. Is the generated code even type safe? Is it synthesizable? What physical resources (e.g. combinatorial gates and flip-flops) does it require? It is often impossible to answer these questions without first generating the fully-expanded code. In the Verilog and VHDL communities, this generation process is referred to as elaboration.

This paper proposes a disciplined approach to elaboration in Verilog. By viewing Verilog as a statically typed two-level language, we are able to reflect the distinction between values that are known at elaboration time and values that are part of the circuit computation. This distinction is crucial for determining whether abstractions such as iteration and module parameters are used in a synthesizable manner. To illustrate this idea, we develop a core calculus for Verilog that we call Featherweight Verilog (FV) and an associated static type system. We formally define a preprocessing step analogous to the elaboration phase of Verilog, and the kinds of errors that can occur during this phase. Finally, we show that a well-typed design cannot cause preprocessing errors, and that the result of its expansion is always a synthesizable circuit.

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New York, NY, USA: ACM Press, 2008. s. 13-20
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URN: urn:nbn:se:hh:diva-14405DOI: 10.1145/1328408.1328416ISI: 000267583600005Scopus ID: 2-s2.0-67649521513ISBN: 978-1-59593-977-7 OAI: oai:DiVA.org:hh-14405DiVA, id: diva2:396139
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2008 ACM SIGPLAN Symposium on Partial Evaluation and Semantics-Based Program Manipulation, San Francisco, California, USA, January 7-8, 2008
Tillgänglig från: 2011-02-08 Skapad: 2011-02-08 Senast uppdaterad: 2018-03-23Bibliografiskt granskad

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