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Two-level Reconfigurable Architecture for High-Performance Signal Processing
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).ORCID-id: 0000-0001-6625-6533
2004 (engelsk)Inngår i: ERSA'04, The 2004 International Conference on Engineering of Reconfigurable Systems and Algorithms: The 2004 International MultiConference in Computer Science and Computer Engineering / [ed] Toomas P. Plaks, Arthens: CSREA Press, 2004, s. 177-183Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

High speed signal processing is often performed as a pipeline of functions on streams or blocks of data. In order to obtain both flexibility and performance, parallel, reconfigurable array structures are suitable for such processing. The array topology can be used both on the micro and macro-levels, i.e. both when mapping a function on a fine-grained array structure and when mapping a set of functions on different nodes in a coarse-grained array. We outline an architecture on the macro-level as well as explore the use of an existing, commercial, word level reconfigurable architecture on the micro-level. We implement an FFT algorithm in order to determine how much of the available resources are needed for controlling the computations. Having no program memory and instruction sequencing available, a large fraction, 70%, of the used resources is used for controlling the computations, but this is still more efficient than having statically dedicated resources for control. Data can stream through the array at maximum I/O rate, while computing FFTs. The paper also shows how pipelining of the FFT algorithm over a two-level reconfigurable array of arrays can be done in various ways, depending on the application demands.

sted, utgiver, år, opplag, sider
Arthens: CSREA Press, 2004. s. 177-183
Emneord [en]
signal processing, reconfigurable array, dataflow
HSV kategori
Identifikatorer
URN: urn:nbn:se:hh:diva-5991ISI: 000225880300024Scopus ID: 2-s2.0-12744261981ISBN: 9781932415421 (tryckt)OAI: oai:DiVA.org:hh-5991DiVA, id: diva2:353083
Konferanse
International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA’04, Las Vegas, Nevada, June 2004
Tilgjengelig fra: 2010-09-23 Laget: 2010-09-23 Sist oppdatert: 2018-03-28bibliografisk kontrollert

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