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A Design Methodology for Resource to Performance Tradeoff Adjustment in FPGAs
LUMS University, DHA Phase-2, Lahore, Pakistan.
Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).ORCID-id: 0000-0002-4932-4036
Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Inbyggda system (CERES).ORCID-id: 0000-0001-6625-6533
2010 (engelsk)Inngår i: FPGAworld '10 Proceedings of the 7th FPGAworld Conference, New York: ACM Press, 2010, s. 14-19Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

When implementing computation-intensive algorithms on finegrained parallel architectures, adjustment of resource to performance tradeoff is a big challenge. This paper proposes a methodology for dealing with some of these performance tradeoffs by adjusting parallelism at different levels. In a case study, interpolation kernels are implemented on a fine-grained architecture (FPGA) using a high level language (Mitrion-C). For both cubic and bi-cubic interpolation, one single-kernel, one cross-kernel and two multi-kernel parallel implementations are designed and evaluated. Our results demonstrate that no single level of parallelism can be used for trade-off adjustment. Instead, the appropriate degree of parallelism on each level, according to available resources and the performance requirements of the application, needs to be found. Basing the design on high-level programming simplifies the trade-off process. This research is a step towards automation of the choice of parallelization based on a combination of parallelism levels.

sted, utgiver, år, opplag, sider
New York: ACM Press, 2010. s. 14-19
HSV kategori
Identifikatorer
URN: urn:nbn:se:hh:diva-5443DOI: 10.1145/1975482.1975483Scopus ID: 2-s2.0-79957774017ISBN: 978-145030481-8 OAI: oai:DiVA.org:hh-5443DiVA, id: diva2:345711
Konferanse
7th FPGAworld Conference, FPGAworld 2010, Copenhagen, 6 September 2010
Tilgjengelig fra: 2010-08-26 Laget: 2010-08-26 Sist oppdatert: 2015-08-21bibliografisk kontrollert

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