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Reconfigurable optical interconnection system supporting concurrent application-specific parallel computing
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0002-6526-3931
2005 (English)In: 17th Symposium on Computer Architecture and High Performance Computing: SBAC-PAD 2005 : proceedings : 24-27 October, 2005, Rio de Janeiro, PR, Brazil / [ed] Claudio L. Amorim, Washington, DC, USA: IEEE Computer Society, 2005, p. 44-51Conference paper, Published paper (Refereed)
Abstract [en]

Application specific architectures are highly desirable in embedded parallel computing systems at the same time as designers strive for using one embedded parallel computing platform for several applications. If this can be achieved, the cost can be decreased in comparison to using several different embedded parallel computing systems. This paper presents a novel approach of running several high-performance applications concurrently on one single parallel computing system. By using a reconfigurable backplane interconnection system, the applications can be run efficiently with high network flexibility since the interconnect network can be adapted to fit the application that is being processed for the moment. More precisely, this paper investigates how the space time adaptive processing (STAP) radar algorithm and the stripmap synthetic aperture radar (SAR) algorithm can be mapped on a multi-cluster processing system with a reconfigurable optical interconnection system realized by a micro-optical-electrical mechanical system (MOEMS) crossbars. The paper describes the reconfigurable platform, the two algorithms and how they individually can be mapped on the targeted multiprocessor system. It is also described how these two applications can be mapped simultaneously on the optical reconfigurable platform. Implications and requirements on communication bandwidth and processor performance in different critical points of the two applications are presented. The results of the analysis show that an implementation is feasible with today's MOEMS technology, and that the two applications can be successfully run in a time-sharing scheme, both at the processing side and at the access for interconnection bandwidth.

Place, publisher, year, edition, pages
Washington, DC, USA: IEEE Computer Society, 2005. p. 44-51
Series
Symposium on Computer Architecture and High Performance Computing. Proceedings, ISSN 1550-6533 ; 2005
Keywords [en]
Embedded systems, Multiprocessor interconnection networks, Optical interconnections, Parallel programming, Reconfigurable architectures
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:hh:diva-414DOI: 10.1109/CAHPC.2005.35Scopus ID: 2-s2.0-33847235068Local ID: 2082/752ISBN: 0-7695-2446-X OAI: oai:DiVA.org:hh-414DiVA, id: diva2:237593
Conference
17th Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2005, 24-27 October, 2005, Rio de Janeiro, Brazil
Note

©2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2007-01-23 Created: 2007-01-23 Last updated: 2018-03-23Bibliographically approved

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CiteExportLink to record
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