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System-Level Runtime Reconfigurablity - Optical Interconnection Networks for Switching Applications
Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).ORCID-id: 0000-0002-6526-3931
2004 (engelsk)Inngår i: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 / [ed] Toomas P Plaks & M Gokhale, Athens, USA: CSREA Press, 2004, s. 155-162Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

The performance requirements on data and telecommunication switches and routers are continuously increasing and it is evident that new ideas and architectures must come to light to satisfy these new demands. In this paper, a runtime reconfigurable modular design approach is presented, using state-of-the-art microoptical-electrical mechanical system (MOEMS) components. The paper introduces a novel field of reconfigurability, where reconfiguration is made on the system level instead of, e.g. fine-granularity reconfigurable logic. Different reconfigurable system solutions with support to adapt for asymmetric traffic patterns are proposed and compared to see how design choices affect flexibility, performance etc. The proposed solutions are characterized by their multistage networks with reconfigurable shuffle patterns.

sted, utgiver, år, opplag, sider
Athens, USA: CSREA Press, 2004. s. 155-162
Emneord [en]
Interconnection networks, Computer networks, Optical interconnection, Switch control
HSV kategori
Identifikatorer
URN: urn:nbn:se:hh:diva-388ISI: 000225880300021Scopus ID: 2-s2.0-12744272379Lokal ID: 2082/712ISBN: 1-932415-42-4 ISBN: 978-193241542-1 OAI: oai:DiVA.org:hh-388DiVA, id: diva2:237567
Konferanse
International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA '04, Las Vegas, Nevada, USA, June 21 - 24, 2004
Tilgjengelig fra: 2007-01-12 Laget: 2007-01-12 Sist oppdatert: 2018-03-23bibliografisk kontrollert
Inngår i avhandling
1. Reconfigurable Optical Interconnection Networks for High-Performance Embedded
Åpne denne publikasjonen i ny fane eller vindu >>Reconfigurable Optical Interconnection Networks for High-Performance Embedded
2005 (engelsk)Licentiatavhandling, med artikler (Annet vitenskapelig)
Abstract [en]

In embedded computer and communication system the capacity demand for interconnection networks is increasing continuously in order to achieve high-performance systems. Recent breakthroughs show that by using reconfigurability inside a single chip substantial performance gains can be added. However, in this thesis the focus is on system level reconfigurability (between chips or modules) and the performance gains that potentially can be achieved by having support for runtime reconfigurability on the system level.This thesis addresses the field of runtime system level reconfigurability with the use of optics in switches and routers for data- and telecommunications, and in multi-processor systems used for embedded signal processing. Several reconfigurable systems for switching and routing with support to adapt for asymmetric traffic patterns are proposed and compared to identify how design choices affect flexibility, performance etc. The proposed solutions are characterized by their multistage optical interconnection networks with reconfigurable shuffle patterns, where the reconfigurability is provided by micro-optical-electrical mechanical systems. More specifically, application-specific bottlenecks can be resolved by reconfiguring the interconnection network according to the current application demands. The benefits of the architectural solutions are confirmed by simulations that clearly show that the architectures can achieve high performance for both symmetric application characteristics and for several classes of asymmetric application characteristics. The final architectural solution is characterized by electronic packet-switches interconnected through an optical backplane, which is reconfigurable. Moreover, the thesis presents how several signal processing applications can be mapped to run concurrently in a time-shared scheme on a single reconfigurable multi-processor system that has high flexibility to adapt for the application currently at hand. The interconnection network is then adapted (reconfigured) according to the demands of the currently executed application in each time instance. The analysis shows that it is feasible to build such a system with today’s components.

sted, utgiver, år, opplag, sider
Göteborg: Chalmers tekniska högskola, 2005. s. 30
Serie
Technical report. L (Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University), ISSN 1652-876X ; 4
Emneord
MOEMS, Micro-optical-electrical mechanical systems, Reconfigurable interconnection networks, Data communication, Telecommunication, Radar signal processing, Asymmetric application, Symmetric application, STAP, SAR, Embedded systems, VCSEL, Parallel processing system, Optical communication
HSV kategori
Identifikatorer
urn:nbn:se:hh:diva-373 (URN)2082/697 (Lokal ID)2082/697 (Arkivnummer)2082/697 (OAI)
Presentation
2005-04-22, Wigfors, Kristian IV:s väg 3, Halmstad, 15:47 (engelsk)
Opponent
Merknad

[Paper D] Agelis, Sacki, "STAP and SAR on an embedded parallel computing system with a reconfigurable interconnection systems," Research Report IDE-0537, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad University, Sweden, 2004

Tilgjengelig fra: 2007-01-10 Laget: 2007-01-10 Sist oppdatert: 2018-03-23bibliografisk kontrollert

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