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The REMAP Reconfigurable Architecture: a Retrospective
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS). Chalmers University of Technology, Gothenburg, Sweden.
Chalmers University of Technology, Gothenburg, Sweden.
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS). Telecommunications Research Center Vienna (FTW), Vienna, Austria.ORCID-id: 0000-0002-0562-2082
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).ORCID-id: 0000-0001-6625-6533
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2006 (Engelska)Ingår i: FPGA Implementations of Neural Networks, New York: Springer-Verlag New York, 2006, s. 325-360Kapitel i bok, del av antologi (Refereegranskat)
Abstract [en]

The goal of the REMAP project was to gain new knowledge about the design and use of massively parallel computer architectures in embedded real-time systems. In order to support adaptive and learning behavior in such systems, the efficient execution of Artificial Neural Network (ANN) algorithms on regular processor arrays was in focus. The REMAP-β parallel computer built in the project was designed with ANN computations as the main target application area. This chapter gives an overview of the computational requirements found in ANN algorithms in general and motivates the use of regular processor arrays for the efficient execution of such algorithms. REMAP-β was implemented using the FPGA circuits that were available around 1990. The architecture, following the SIMD principle (Single Instruction stream, Multiple Data streams), is described, as well as the mapping of some important and representative ANN algorithms. Implemented in FPGA, the system served as an architecture laboratory. Variations of the architecture are discussed, as well as scalability of fully synchronous SIMD architectures. The design principles of a VLSI-implemented successor of REMAP-β are described, and the paper is concluded with a discussion of how the more powerful FPGA circuits of today could be used in a similar architecture. © 2006 Springer.

Ort, förlag, år, upplaga, sidor
New York: Springer-Verlag New York, 2006. s. 325-360
Nyckelord [en]
Artificial neural networks, parallel architecture, SIMD, field-programmable gate arrays (FPGA)
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URN: urn:nbn:se:hh:diva-377DOI: 10.1007/0-387-28487-7_12Scopus ID: 2-s2.0-84889954052Lokalt ID: 2082/701ISBN: 0-387-28485-0 (tryckt)OAI: oai:DiVA.org:hh-377DiVA, id: diva2:237556
Tillgänglig från: 2007-01-10 Skapad: 2007-01-10 Senast uppdaterad: 2018-03-23Bibliografiskt granskad

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Bengtsson, LarsNordström, TomasSvensson, Bertil

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Halmstad Embedded and Intelligent Systems Research (EIS)Centrum för forskning om inbyggda system (CERES)
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