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A Configurable Two Dimensional Mesh Network-on-Chip Implementation in Chisel
Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0001-8652-0098
Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).ORCID iD: 0000-0002-4932-4036
RISE Research Institutes of Sweden, Gothenburg, Sweden.ORCID iD: 0000-0002-0562-2082
2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

On-chip communication plays a significant role in the performance of manycore architectures. Therefore, they require a proper on-chip communication infrastructure that can scale with the number of the cores. As a solution, network-on-chip structures have emerged and are being used.

This paper presents description of a two dimensional mesh network-on-chip router and a network interface, which are implemented in Chisel to be integrated to the rocket chip generator that generates RISC-V (rocket) cores. The router is implemented in VHDL as well and the two implementations are verified and compared.

Hardware resource usage and performance of different sized networks are analyzed. The implementations are synthesized for a Xilinx Ultrascale FPGA via Xilinx tools for the hardware resource usage and clock frequency results. The performance results including latency and throughput measurements with different traffic patterns, are collected with cycle accurate emulations. 

The implementations in Chisel and VHDL do not show a significant difference. Chisel requires around 10% fewer lines of code, however, the difference in the synthesis results is negligible. Our latency result are better than the majority of the other studies. The other results such as hardware usage, clock frequency, and throughput are competitive when compared to the related works.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2019.
Keywords [en]
network-on-chip, Chisel, mesh, scalable
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:hh:diva-39324OAI: oai:DiVA.org:hh-39324DiVA, id: diva2:1314190
Conference
32nd IEEE International System-on-Chip Conference (SOCC), Singapore, September 3-6, 2019
Part of project
Towards Next Generation Embedded Systems: Utilizing Parallelism and Reconfigurability, Vinnova
Funder
Vinnova
Note

©2019 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2019-05-07 Created: 2019-05-07 Last updated: 2019-10-10
In thesis
1. Hardware/Software Co-Design of Heterogeneous Manycore Architectures
Open this publication in new window or tab >>Hardware/Software Co-Design of Heterogeneous Manycore Architectures
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In the era of big data, advanced sensing, and artificial intelligence, the required computation power is provided mostly by multicore and manycore architectures. However, the performance demand keeps growing. Thus the computer architectures need to continue evolving and provide higher performance. The applications, which are executed on the manycore architectures, are divided into several tasks to be mapped on separate cores and executed in parallel. Usually these tasks are not identical and may be executed more efficiently on different types of cores within a heterogeneous architecture. Therefore, we believe that the heterogeneous manycores are the next step for the computer architectures. However, there is a lack of knowledge on what form of heterogeneity is the best match for a given application or application domain. This knowledge can be acquired through designing these architectures and testing different design configurations. However, designing these architectures is a great challenge. Therefore, there is a need for an automated design method to facilitate the architecture design and design space exploration to gather knowledge on architectures with different configurations. Additionally, it is already difficult to program manycore architectures efficiently and this difficulty will only increase further with the introduction of heterogeneity due to the increase in the complexity of the architectures, unless this complexity is somehow hidden. There is a need for software development tools to facilitate the software development for these architectures and enable portability of the same software across different manycore platforms.

In this thesis, we first address the challenges of the software development for manycore architectures. We evaluate a dataflow language (CAL) and a source-to-source compilation framework (Cal2Many) with several case studies in order to reveal their impact on productivity and performance of the software. The language supports task level parallelism by adopting actor model and the framework takes CAL code and generates implementations in the native language of several different architectures.

In order to address the challenge of custom hardware development, we first evaluate a commercial manycore architecture namely Epiphany and identify its demerits. Then we study manycore architectures in order to reveal possible uses of heterogeneity in manycores and facilitate choice of architecture for software and hardware development. We define a taxonomy for manycore architectures that is based on the levels of heterogeneity they contain and discuss the benefits and drawbacks of these levels. We finally develop and evaluate a design method to design heterogeneous manycore architectures customized based on application requirements. The architectures designed with this method consist of cores with application specific accelerators. The majority of the design method is automated with software tools, which support different design configurations in order to increase the productivity of the hardware developer and enable design space exploration.

Our results show that the dataflow language, together with the software development tool, decreases software development efforts significantly (25-50%), while having a small impact (2-17%) on the performance. The evaluation of the design method reveal that the performance of automatically generated accelerators is between 96-100% of the performance of their manually developed counterparts. Additionally, it is possible to increase the performance of the architectures by increasing the number of cores and using application specific accelerators, usually with a cost on the area usage. However, under certain circumstances, using accelerator may lead to avoiding usage of large general purpose components such as the floating-point unit and therefore improves the area utilization. Eventually, the final impact on the performance and area usage depends on the configurations. When compared to the Epiphany architecture, which is a commercial homogeneous manycore, the generated manycores show competitive results. We can conclude that the automated design method simplifies heterogeneous manycore architecture design and facilitates design space exploration with the use of configurable parameters.

Place, publisher, year, edition, pages
Halmstad: Halmstad University Press, 2019. p. 205
Series
Halmstad University Dissertations ; 57
Keywords
hardware/software co-design, manycore architectures, heterogeneous manycores, processor design, parallel computing, high performance computing
National Category
Computer Systems Embedded Systems
Identifiers
urn:nbn:se:hh:diva-39325 (URN)978-91-88749-22-2 (ISBN)978-91-88749-23-9 (ISBN)
Public defence
2019-05-28, Wigforssalen, Visionen, Kristian IV:s väg 3, Halmstad, 13:15 (English)
Opponent
Supervisors
Projects
HIPEC - High Performance Embedded ComputingESCHER
Funder
VinnovaKnowledge FoundationSwedish Foundation for Strategic Research
Available from: 2019-05-08 Created: 2019-05-07 Last updated: 2019-05-08Bibliographically approved

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