Router i VHDL 2004 (svensk)Independent thesis Basic level (degree of Bachelor)Oppgave

Abstract [sv]

The purpose of this project has been to construct a router element to be written in VHDL and implemented on a FPGA. Using the router element a networking structure has been constructed where every router element in the network is attached to a logical device, i.e. a processor. The project has been conducted in cooperation with CC-lab on the university in Halmstad where the router element will be used for research and educational purposes. The main demands have been to prioritize transmission speed and that several messages should be able to be sent simultaneously. An additional demand has been that the constructed element should have the capacity to address up to 1024 other router elements. Additionally, features to avoid deadlock in the network has been implemented. Other features are, but not limited to, worm hole routing, authentication by handshaking, crossbar and support for parallel transmissions. The developed router element consists of five communication modules as well as a crossbar to link input ports to output ports. To help avoid deadlocks a queue system has been implemented. The router element has been developed and tested according to the demands put upon it by CC-lab. Unfortunately an interface between the router element and a logical device has not been constructed. The maximum clock frequency of a router element has been established to be 54.6 MHz and working at this speed a transmission capacity of 1.45 Gb/s is reached when 32 bits data width was used.

sted, utgiver, år, opplag, sider

2004.

Emneord [sv]

Network NoC FPGA VHDL routing router SoC System

Identifikatorer

URN: urn:nbn:se:hh:diva-11866Lokal ID: U10899OAI: oai:DiVA.org:hh-11866DiVA, id: diva2:367007

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Denna uppsats kan beställas från arkivet / This paper can be ordered from the archive. Kontakta / Contact: arkivet@hh.seTilgjengelig fra: 2010-11-09 Laget: 2010-11-09bibliografisk kontrollert

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