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Reconfigurable Optical Interconnection Networks for High-Performance Embedded
Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), Halmstad Embedded and Intelligent Systems Research (EIS).
2005 (engelsk)Licentiatavhandling, med artikler (Annet vitenskapelig)
Abstract [en]

In embedded computer and communication system the capacity demand for interconnection networks is increasing continuously in order to achieve high-performance systems. Recent breakthroughs show that by using reconfigurability inside a single chip substantial performance gains can be added. However, in this thesis the focus is on system level reconfigurability (between chips or modules) and the performance gains that potentially can be achieved by having support for runtime reconfigurability on the system level.This thesis addresses the field of runtime system level reconfigurability with the use of optics in switches and routers for data- and telecommunications, and in multi-processor systems used for embedded signal processing. Several reconfigurable systems for switching and routing with support to adapt for asymmetric traffic patterns are proposed and compared to identify how design choices affect flexibility, performance etc. The proposed solutions are characterized by their multistage optical interconnection networks with reconfigurable shuffle patterns, where the reconfigurability is provided by micro-optical-electrical mechanical systems. More specifically, application-specific bottlenecks can be resolved by reconfiguring the interconnection network according to the current application demands. The benefits of the architectural solutions are confirmed by simulations that clearly show that the architectures can achieve high performance for both symmetric application characteristics and for several classes of asymmetric application characteristics. The final architectural solution is characterized by electronic packet-switches interconnected through an optical backplane, which is reconfigurable. Moreover, the thesis presents how several signal processing applications can be mapped to run concurrently in a time-shared scheme on a single reconfigurable multi-processor system that has high flexibility to adapt for the application currently at hand. The interconnection network is then adapted (reconfigured) according to the demands of the currently executed application in each time instance. The analysis shows that it is feasible to build such a system with today’s components.

sted, utgiver, år, opplag, sider
Göteborg: Chalmers tekniska högskola , 2005. , s. 30
Serie
Technical report. L (Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University), ISSN 1652-876X ; 4
Emneord [en]
MOEMS, Micro-optical-electrical mechanical systems, Reconfigurable interconnection networks, Data communication, Telecommunication, Radar signal processing, Asymmetric application, Symmetric application, STAP, SAR, Embedded systems, VCSEL, Parallel processing system, Optical communication
HSV kategori
Identifikatorer
URN: urn:nbn:se:hh:diva-373Lokal ID: 2082/697OAI: oai:DiVA.org:hh-373DiVA, id: diva2:237552
Presentation
2005-04-22, Wigfors, Kristian IV:s väg 3, Halmstad, 15:47 (engelsk)
Opponent
Merknad

[Paper D] Agelis, Sacki, "STAP and SAR on an embedded parallel computing system with a reconfigurable interconnection systems," Research Report IDE-0537, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad University, Sweden, 2004

Tilgjengelig fra: 2007-01-10 Laget: 2007-01-10 Sist oppdatert: 2018-03-23bibliografisk kontrollert
Delarbeid
1. System-Level Runtime Reconfigurablity - Optical Interconnection Networks for Switching Applications
Åpne denne publikasjonen i ny fane eller vindu >>System-Level Runtime Reconfigurablity - Optical Interconnection Networks for Switching Applications
2004 (engelsk)Inngår i: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 / [ed] Toomas P Plaks & M Gokhale, Athens, USA: CSREA Press, 2004, s. 155-162Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

The performance requirements on data and telecommunication switches and routers are continuously increasing and it is evident that new ideas and architectures must come to light to satisfy these new demands. In this paper, a runtime reconfigurable modular design approach is presented, using state-of-the-art microoptical-electrical mechanical system (MOEMS) components. The paper introduces a novel field of reconfigurability, where reconfiguration is made on the system level instead of, e.g. fine-granularity reconfigurable logic. Different reconfigurable system solutions with support to adapt for asymmetric traffic patterns are proposed and compared to see how design choices affect flexibility, performance etc. The proposed solutions are characterized by their multistage networks with reconfigurable shuffle patterns.

sted, utgiver, år, opplag, sider
Athens, USA: CSREA Press, 2004
Emneord
Interconnection networks, Computer networks, Optical interconnection, Switch control
HSV kategori
Identifikatorer
urn:nbn:se:hh:diva-388 (URN)000225880300021 ()2-s2.0-12744272379 (Scopus ID)2082/712 (Lokal ID)1-932415-42-4 (ISBN)978-193241542-1 (ISBN)2082/712 (Arkivnummer)2082/712 (OAI)
Konferanse
International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA '04, Las Vegas, Nevada, USA, June 21 - 24, 2004
Tilgjengelig fra: 2007-01-12 Laget: 2007-01-12 Sist oppdatert: 2018-03-23bibliografisk kontrollert
2. Visualizing the Potential of Reconfigurable Shuffle-Patterns in Optoelectronic Routers by the Use of MOEMS
Åpne denne publikasjonen i ny fane eller vindu >>Visualizing the Potential of Reconfigurable Shuffle-Patterns in Optoelectronic Routers by the Use of MOEMS
2004 (engelsk)Inngår i: Proceedings of the IASTED International Conference Communication Systems and Networks / [ed] Salvador C.E.P., Calgary, Canada: ACTA Press, 2004, s. 148-154Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

A reconfigurable high performance multistage router architecture is presented and simulated. The router backbone network is an optical shuffle exchange network that has the power of reconfigurability through the use of micro-optical-electrical mechanical systems (MOEMS). The router is subjected to different application classes. The application classes have different characteristics in terms of symmetric/asymmetric traffic properties. We compare our reconfigurable shuffle-pattern for all three application classes for the specified router architecture.

sted, utgiver, år, opplag, sider
Calgary, Canada: ACTA Press, 2004
Emneord
MOEMS, VCSEL, Switch, Router, Application, Reconfigurability
HSV kategori
Identifikatorer
urn:nbn:se:hh:diva-391 (URN)000228555100027 ()2-s2.0-11144308898 (Scopus ID)2082/715 (Lokal ID)0-88986-450-0 (ISBN)2082/715 (Arkivnummer)2082/715 (OAI)
Konferanse
International Conference on Communications Systems and Networks (CSN'2004), Marbella, Spain, Sept. 1-3, 2004
Tilgjengelig fra: 2007-01-12 Laget: 2007-01-12 Sist oppdatert: 2018-03-23bibliografisk kontrollert
3. Optoelectronic router with MOEMS–based reconfigurable shuffle network
Åpne denne publikasjonen i ny fane eller vindu >>Optoelectronic router with MOEMS–based reconfigurable shuffle network
2004 (engelsk)Konferansepaper, Publicerat paper (Fagfellevurdert)
Emneord
optical interconnection networks
HSV kategori
Identifikatorer
urn:nbn:se:hh:diva-2759 (URN)2082/3161 (Lokal ID)2082/3161 (Arkivnummer)2082/3161 (OAI)
Konferanse
Swedish National Computer Networking Workshop (SNCNW’04), Karlstad, Sweden, Nov. 23-24, 2004
Tilgjengelig fra: 2009-08-13 Laget: 2009-08-13 Sist oppdatert: 2018-03-23bibliografisk kontrollert

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