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Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).ORCID-id: 0000-0001-8652-0098
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).ORCID-id: 0000-0003-4828-7488
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).ORCID-id: 0000-0002-0562-2082
Högskolan i Halmstad, Akademin för informationsteknologi, Halmstad Embedded and Intelligent Systems Research (EIS), Centrum för forskning om inbyggda system (CERES).ORCID-id: 0000-0002-4932-4036
2017 (engelsk)Inngår i: 2017 IEEE Computer Society Annual Symposium on VLSI: ISVLSI 2017 / [ed] Michael Hübner, Ricardo Reis, Mircea Stan & Nikolaos Voros, Los Alamitos: IEEE, 2017Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

This paper proposes a novel method for performing division on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is based on an inverter, implemented as a combination of Parabolic Synthesis and second-degree interpolation, followed by a multiplier. It is implemented with and without pipeline stages individually and synthesized while targeting a Xilinx Ultrascale FPGA.

The implementations show better resource usage and latency results when compared to other implementations based on different methods. In case of throughput, the proposed method outperforms most of the other works, however, some Altera FPGAs achieve higher clock rate due to the differences in the DSP slice multiplier design.

Due to the small size, low latency and high throughput, the presented floating-point division unit is suitable for high performance embedded systems and can be integrated into accelerators or be used as a stand-alone accelerator.

sted, utgiver, år, opplag, sider
Los Alamitos: IEEE, 2017.
Serie
IEEE Computer Society Annual Symposium on VLSI, ISSN 2159-3477
Emneord [en]
Floating-point, single precision, division, FPGA, Harmonized Parabolic Synthesis
HSV kategori
Identifikatorer
URN: urn:nbn:se:hh:diva-33793DOI: 10.1109/ISVLSI.2017.28Scopus ID: 2-s2.0-85027258772ISBN: 978-1-5090-6762-6 (digital)ISBN: 978-1-5090-6763-3 (tryckt)OAI: oai:DiVA.org:hh-33793DiVA, id: diva2:1093338
Konferanse
IEEE Computer Society Annual Symposium on VLSI, July 3-5, 2017, Bochum, Germany
Prosjekter
NGES
Forskningsfinansiär
VINNOVATilgjengelig fra: 2017-05-05 Laget: 2017-05-05 Sist oppdatert: 2019-05-07bibliografisk kontrollert
Inngår i avhandling
1. Utilizing Heterogeneity in Manycore Architectures for Streaming Applications
Åpne denne publikasjonen i ny fane eller vindu >>Utilizing Heterogeneity in Manycore Architectures for Streaming Applications
2017 (engelsk)Licentiatavhandling, med artikler (Annet vitenskapelig)
Abstract [en]

In the last decade, we have seen a transition from single-core to manycore in computer architectures due to performance requirements and limitations in power consumption and heat dissipation. The first manycores had homogeneous architectures consisting of a few identical cores. However, the applications, which are executed on these architectures, usually consist of several tasks requiring different hardware resources to be executed efficiently. Therefore, we believe that utilizing heterogeneity in manycores will increase the efficiency of the architectures in terms of performance and power consumption. However, development of heterogeneous architectures is more challenging and the transition from homogeneous to heterogeneous architectures will increase the difficulty of efficient software development due to the increased complexity of the architecture. In order to increase the efficiency of hardware and software development, new hardware design methods and software development tools are required. Additionally, there is a lack of knowledge on the performance of applications when executed on manycore architectures.

The transition began with a shift from single-core architectures to homogeneous multicore architectures consisting of a few identical cores. It now continues with a shift from homogeneous architectures with identical cores to heterogeneous architectures with different types of cores specialized for different purposes. However, this transition has increased the complexity of architectures and hence the complexity of software development and execution. In order to decrease the complexity of software development, new software tools are required. Additionally, there is a lack of knowledge on what kind of heterogeneous manycore design is most efficient for different applications and what are the performances of these applications when executed on current commercial manycores.

This thesis studies manycore architectures in order to reveal possible uses of heterogeneity in manycores and facilitate choice of architecture for software and hardware developers. It defines a taxonomy for manycore architectures that is based on the levels of heterogeneity they contain and discusses benefits and drawbacks of these levels. Additionally, it evaluates several applications, a dataflow language (CAL), a source-to-source compilation framework (Cal2Many), and a commercial manycore architecture (Epiphany). The compilation framework takes implementations written in the dataflow language as input and generates code targetting different manycore platforms. Based on these evaluations, the thesis identifies the bottlenecks of the architecture. It finally presents a methodology for developing heterogeneoeus manycore architectures which target specific application domains.

Our studies show that using different types of cores in manycore architectures has the potential to increase the performance of streaming applications. If we add specialized hardware blocks to a core, the performance easily increases by 15x for the target application while the core size increases by 40-50% which can be optimized further. Other results prove that dataflow languages, together with software development tools, decrease software development efforts significantly (25-50%) while having a small impact (2-17%) on the performance.

sted, utgiver, år, opplag, sider
Halmstad: Halmstad University Press, 2017. s. 78
Serie
Halmstad University Dissertations ; 29
Emneord
Manycores, parallel architectures, parallelism, streaming applications, dataflow, manycore design, heterogeneous manycores
HSV kategori
Identifikatorer
urn:nbn:se:hh:diva-33792 (URN)978-91-87045-60-8 (ISBN)978-91-87045-61-5 (ISBN)
Presentation
2017-06-02, Wigforss, Kristian IV:s väg 3, Halmstad, 13:15 (engelsk)
Opponent
Veileder
Prosjekter
HiPEC (High Performance Embedded Computing)NGES (Towards Next Generation Embedded Systems: Utilizing Parallelism and Reconfigurability)
Forskningsfinansiär
VINNOVASwedish Foundation for Strategic Research
Tilgjengelig fra: 2017-05-09 Laget: 2017-05-05 Sist oppdatert: 2017-05-09bibliografisk kontrollert
2. Hardware/Software Co-Design of Heterogeneous Manycore Architectures
Åpne denne publikasjonen i ny fane eller vindu >>Hardware/Software Co-Design of Heterogeneous Manycore Architectures
2019 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

In the era of big data, advanced sensing, and artificial intelligence, the required computation power is provided mostly by multicore and manycore architectures. However, the performance demand keeps growing. Thus the computer architectures need to continue evolving and provide higher performance. The applications, which are executed on the manycore architectures, are divided into several tasks to be mapped on separate cores and executed in parallel. Usually these tasks are not identical and may be executed more efficiently on different types of cores within a heterogeneous architecture. Therefore, we believe that the heterogeneous manycores are the next step for the computer architectures. However, there is a lack of knowledge on what form of heterogeneity is the best match for a given application or application domain. This knowledge can be acquired through designing these architectures and testing different design configurations. However, designing these architectures is a great challenge. Therefore, there is a need for an automated design method to facilitate the architecture design and design space exploration to gather knowledge on architectures with different configurations. Additionally, it is already difficult to program manycore architectures efficiently and this difficulty will only increase further with the introduction of heterogeneity due to the increase in the complexity of the architectures, unless this complexity is somehow hidden. There is a need for software development tools to facilitate the software development for these architectures and enable portability of the same software across different manycore platforms.

In this thesis, we first address the challenges of the software development for manycore architectures. We evaluate a dataflow language (CAL) and a source-to-source compilation framework (Cal2Many) with several case studies in order to reveal their impact on productivity and performance of the software. The language supports task level parallelism by adopting actor model and the framework takes CAL code and generates implementations in the native language of several different architectures.

In order to address the challenge of custom hardware development, we first evaluate a commercial manycore architecture namely Epiphany and identify its demerits. Then we study manycore architectures in order to reveal possible uses of heterogeneity in manycores and facilitate choice of architecture for software and hardware development. We define a taxonomy for manycore architectures that is based on the levels of heterogeneity they contain and discuss the benefits and drawbacks of these levels. We finally develop and evaluate a design method to design heterogeneous manycore architectures customized based on application requirements. The architectures designed with this method consist of cores with application specific accelerators. The majority of the design method is automated with software tools, which support different design configurations in order to increase the productivity of the hardware developer and enable design space exploration.

Our results show that the dataflow language, together with the software development tool, decreases software development efforts significantly (25-50%), while having a small impact (2-17%) on the performance. The evaluation of the design method reveal that the performance of automatically generated accelerators is between 96-100% of the performance of their manually developed counterparts. Additionally, it is possible to increase the performance of the architectures by increasing the number of cores and using application specific accelerators, usually with a cost on the area usage. However, under certain circumstances, using accelerator may lead to avoiding usage of large general purpose components such as the floating-point unit and therefore improves the area utilization. Eventually, the final impact on the performance and area usage depends on the configurations. When compared to the Epiphany architecture, which is a commercial homogeneous manycore, the generated manycores show competitive results. We can conclude that the automated design method simplifies heterogeneous manycore architecture design and facilitates design space exploration with the use of configurable parameters.

sted, utgiver, år, opplag, sider
Halmstad: Halmstad University Press, 2019. s. 205
Serie
Halmstad University Dissertations ; 57
Emneord
hardware/software co-design, manycore architectures, heterogeneous manycores, processor design, parallel computing, high performance computing
HSV kategori
Identifikatorer
urn:nbn:se:hh:diva-39325 (URN)978-91-88749-22-2 (ISBN)978-91-88749-23-9 (ISBN)
Disputas
2019-05-28, Wigforssalen, Visionen, Kristian IV:s väg 3, Halmstad, 13:15 (engelsk)
Opponent
Veileder
Prosjekter
HIPEC - High Performance Embedded ComputingESCHER
Forskningsfinansiär
VinnovaKnowledge FoundationSwedish Foundation for Strategic Research
Tilgjengelig fra: 2019-05-08 Laget: 2019-05-07 Sist oppdatert: 2019-05-08bibliografisk kontrollert

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