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Title [sv]
Mot nästa generation inbyggda system: användning av parallellism och rekonfigurerbarhet
Title [en]
Towards Next Generation Embedded Systems: Utilizing Parallelism and Reconfigurability
Abstract [sv]
Den stora variationen av tillämpningar och prestandakrav för inbyggda system gör att nya plattformar - anpassade till kraven - måste användas. Mångkärniga processorer och rekonfigurerbar hårdvara krävs ofta, vilket innebär nya arkitekturer och krav på nya, tidseffektiva programmeringsmetoder som möjliggör att tillämpningsprogramvaran kan flyttas mellan plattformar. De båda forskningsgrupperna, vid Högskolan i Halmstad (HH) respektive Amrita University, Bangalore (AMU), har kompletterande kompetenser för att ta fram arkitekturer och programmeringsmiljöer för sådana plattformar och utvärdera dem i industriella tillämpningar. Tre företag och ett industriforskningsinstitut utgör samarbetspartnerna för kravställande, dialog och utvärdering samt för att sprida resultat och metoder i näringslivet. Realtidskrav, låg energiförbrukning och låg kostnad är krav som finns i tillämpningarna, och de möts med flexibla arkitekturer och enkla programmeringssätt, allt i syfte att förkorta time-to-market.De båda forskargrupperna präglas av stor industrirelevans och -samarbete. Forskningsledaren på den indiska sidan har haft kontakter med den svenska gruppen i flera år, bland annat vid arbete vid europeiska universitet. Hon håller nu på att bygga upp forskningen inom inbyggda system vid Amrita University; detta kommer att ske i stark samverkan med HH samt företag i såväl AMU:s som HH:s nätverk. Det ökade samarbetet mellan HH och AMU kommer att gynna master- och forskarutbildningen på båda sidor.
Abstract [en]
The wide variety of applications and performance requirements for embedded systems requires new platforms, tailored to requirements, to be used. Manycore processors and reconfigurable hardware is required, which means new architectures and a need for new, time-efficient programming methods that can enable application software to be easily ported between platforms. The two research groups, at Halmstad University (HH) and Amrita University, Bangalore (AMU), have complementary competencies to develop architectures and programming environments for such platforms and evaluate them in industrial applications. Three companies and one industrial research institute are partners for requirements specification, dialogue and evaluation, and help disseminate results and methods in industry. Real-time demands, low power consumption and low cost are requirements of the applications, and they are met with flexible architectures and simplified programming, all in order to shorten time-to-market.The two research groups are characterized by high industrial relevance and cooperation with industry. The research leader on the Indian side has had contacts with the Swedish group for several years, including while working at European universities. She is now building up research in embedded systems at Amrita University in Bangalore; this will be done in close collaboration with HH as well as enterprises in both AMU´s HH´s networks. The increased cooperation between HH and AMU will benefit the master and postgraduate education on both sides.
Publications (4 of 4) Show all publications
Savas, S., Ul-Abdin, Z. & Nordström, T. (2019). A Configurable Two Dimensional Mesh Network-on-Chip Implementation in Chisel. In: : . Paper presented at IEEE International System-on-Chip Conference (SOCC), Singapore, September 3-6, 2019. IEEE conference proceedings
Open this publication in new window or tab >>A Configurable Two Dimensional Mesh Network-on-Chip Implementation in Chisel
2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

On-chip communication plays a significant role in the performance of manycore architectures. Therefore, they require a proper on-chip communication infrastructure that can scale with the number of the cores. As a solution, network-on-chip structures have emerged and are being used.

This paper presents description of a two dimensional mesh network-on-chip router and a network interface, which are implemented in Chisel to be integrated to the rocket chip generator that generates RISC-V (rocket) cores. The router is implemented in VHDL as well and the two implementations are verified and compared.

Hardware resource usage and performance of different sized networks are analyzed. The implementations are synthesized for a Xilinx Ultrascale FPGA via Xilinx tools for the hardware resource usage and clock frequency results. The performance results including latency and throughput measurements with different traffic patterns, are collected with cycle accurate emulations. 

The implementations in Chisel and VHDL do not show a significant difference. Chisel requires around 10% fewer lines of code, however, the difference in the synthesis results is negligible.Our latency result are better than the majority of the other studies. The other results such as hardware usage, clock frequency, and throughput are competitive when compared to the related works.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2019
Keywords
network-on-chip, Chisel, mesh, scalable
National Category
Computer Systems Embedded Systems
Identifiers
urn:nbn:se:hh:diva-39324 (URN)
Conference
IEEE International System-on-Chip Conference (SOCC), Singapore, September 3-6, 2019
Funder
Vinnova
Available from: 2019-05-07 Created: 2019-05-07 Last updated: 2019-05-08
Savas, S., Ul-Abdin, Z. & Nordström, T. (2019). A Framework to Generate Domain-Specific Manycore Architectures from Dataflow Programs. Microprocessors and microsystems
Open this publication in new window or tab >>A Framework to Generate Domain-Specific Manycore Architectures from Dataflow Programs
2019 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436Article in journal (Refereed) Submitted
Abstract [en]

In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures.

However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method allows generation of manycore architectures with different configurations including core augmentation through instruction extensions and custom accelerators. The method starts from developing applications in a high-level dataflow language and ends by generating synthesizable Verilog code and cycle accurate emulator for the generated architecture.

We evaluate the design method and the software tools by generating several architectures specialized for two different applications and measure their performance and hardware resource usages. Our results show that the design method can be used to generate specialized manycore architectures targeting applications from different domains. The specialized architectures show at least 3 to 4 times better performance than the general purpose counterparts. In certain cases, replacing general purpose components with specialized components saves hardware resources. Automating the method increases the speed of architecture development and facilitates the design space exploration of manycore architectures.

Place, publisher, year, edition, pages
Amsterdam: Elsevier, 2019
Keywords
Domain-specific, multicore, manycore, accelerator, code generation, hardware/software co-design
National Category
Computer Systems Embedded Systems Signal Processing
Identifiers
urn:nbn:se:hh:diva-39323 (URN)
Funder
Vinnova
Available from: 2019-05-07 Created: 2019-05-07 Last updated: 2019-05-08
Savas, S. (2019). Hardware/Software Co-Design of Heterogeneous Manycore Architectures. (Doctoral dissertation). Halmstad: Halmstad University Press
Open this publication in new window or tab >>Hardware/Software Co-Design of Heterogeneous Manycore Architectures
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In the era of big data, advanced sensing, and artificial intelligence, the required computation power is provided mostly by multicore and manycore architectures. However, the performance demand keeps growing. Thus the computer architectures need to continue evolving and provide higher performance. The applications, which are executed on the manycore architectures, are divided into several tasks to be mapped on separate cores and executed in parallel. Usually these tasks are not identical and may be executed more efficiently on different types of cores within a heterogeneous architecture. Therefore, we believe that the heterogeneous manycores are the next step for the computer architectures. However, there is a lack of knowledge on what form of heterogeneity is the best match for a given application or application domain. This knowledge can be acquired through designing these architectures and testing different design configurations. However, designing these architectures is a great challenge. Therefore, there is a need for an automated design method to facilitate the architecture design and design space exploration to gather knowledge on architectures with different configurations. Additionally, it is already difficult to program manycore architectures efficiently and this difficulty will only increase further with the introduction of heterogeneity due to the increase in the complexity of the architectures, unless this complexity is somehow hidden. There is a need for software development tools to facilitate the software development for these architectures and enable portability of the same software across different manycore platforms.

In this thesis, we first address the challenges of the software development for manycore architectures. We evaluate a dataflow language (CAL) and a source-to-source compilation framework (Cal2Many) with several case studies in order to reveal their impact on productivity and performance of the software. The language supports task level parallelism by adopting actor model and the framework takes CAL code and generates implementations in the native language of several different architectures.

In order to address the challenge of custom hardware development, we first evaluate a commercial manycore architecture namely Epiphany and identify its demerits. Then we study manycore architectures in order to reveal possible uses of heterogeneity in manycores and facilitate choice of architecture for software and hardware development. We define a taxonomy for manycore architectures that is based on the levels of heterogeneity they contain and discuss the benefits and drawbacks of these levels. We finally develop and evaluate a design method to design heterogeneous manycore architectures customized based on application requirements. The architectures designed with this method consist of cores with application specific accelerators. The majority of the design method is automated with software tools, which support different design configurations in order to increase the productivity of the hardware developer and enable design space exploration.

Our results show that the dataflow language, together with the software development tool, decreases software development efforts significantly (25-50%), while having a small impact (2-17%) on the performance. The evaluation of the design method reveal that the performance of automatically generated accelerators is between 96-100% of the performance of their manually developed counterparts. Additionally, it is possible to increase the performance of the architectures by increasing the number of cores and using application specific accelerators, usually with a cost on the area usage. However, under certain circumstances, using accelerator may lead to avoiding usage of large general purpose components such as the floating-point unit and therefore improves the area utilization. Eventually, the final impact on the performance and area usage depends on the configurations. When compared to the Epiphany architecture, which is a commercial homogeneous manycore, the generated manycores show competitive results. We can conclude that the automated design method simplifies heterogeneous manycore architecture design and facilitates design space exploration with the use of configurable parameters.

Place, publisher, year, edition, pages
Halmstad: Halmstad University Press, 2019. p. 205
Series
Halmstad University Dissertations ; 57
Keywords
hardware/software co-design, manycore architectures, heterogeneous manycores, processor design, parallel computing, high performance computing
National Category
Computer Systems Embedded Systems
Identifiers
urn:nbn:se:hh:diva-39325 (URN)978-91-88749-22-2 (ISBN)978-91-88749-23-9 (ISBN)
Public defence
2019-05-28, Wigforssalen, Visionen, Kristian IV:s väg 3, Halmstad, 13:15 (English)
Opponent
Supervisors
Projects
HIPEC - High Performance Embedded ComputingESCHER
Funder
VinnovaKnowledge FoundationSwedish Foundation for Strategic Research
Available from: 2019-05-08 Created: 2019-05-07 Last updated: 2019-05-08Bibliographically approved
Savas, S., Yassin, A., Nordström, T. & Ul-Abdin, Z. (2019). Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit. In: : . Paper presented at International Symposium on VLSI Design (ISVLSI), Miami, Florida, USA, July 15-17, 2019. IEEE conference proceedings
Open this publication in new window or tab >>Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit
2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

This paper proposes a novel method for performing square root operation on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is implemented using Harmonized Parabolic Synthesis. It is implemented with and without pipeline stages individually and synthesized for two different Xilinx FPGA boards.

The implementations show better resource usage and latency results when compared to other similar works including Xilinx intellectual property (IP) that uses the CORDIC method. Any method calculating the square root will make approximation errors. Unless these errors are distributed evenly around zero, they can accumulate and give a biased result. An attractive feature of the proposed method is the fact that it distributes the errors evenly around zero, in contrast to CORDIC for instance.

Due to the small size, low latency, high throughput, and good error properties, the presented floating-point square root unit is suitable for high performance embedded systems. It can be integrated into a processor’s floating point unit or be used as astand-alone accelerator.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2019
Keywords
square root, floating-point, harmonized parabolic synthesis, fpga, hardware
National Category
Embedded Systems Computer Systems
Identifiers
urn:nbn:se:hh:diva-39322 (URN)
Conference
International Symposium on VLSI Design (ISVLSI), Miami, Florida, USA, July 15-17, 2019
Funder
Vinnova
Available from: 2019-05-07 Created: 2019-05-07 Last updated: 2019-08-02
Principal InvestigatorUl-Abdin, Zain
Coordinating organisation
Halmstad University
Funder
Period
2015-12-01 - 2019-08-31
National Category
Embedded Systems
Identifiers
DiVA, id: project:241Project, id: 2015-04178_Vinnova

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